MFS5600AMBA0ES datasheet(51/111 Pages) NXP

51 / 111 page

NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

17.11 Fault error counter

A fault error counter is implemented to count the number of faults occurring in the

application and based on system reaction. The limit value of the fault error counter is

programmable using the FLT_ERR_CNT_LIMIT[1:0] bits.

Note: “FLT_ERR_CNT_LIMIT[1:0]” should be initialized in the application once during

system power-up. Changing it during normal operation may reset the FLT_ERR_CNT

value.

FLT_ERR_CNT_LIMIT[1:0]

Configure the maximum value of the Fault

error counter

Max value = 1

01 (Reset State)

Max value = 2

Max value = 6

Max value = 12

Table 49. FLT_ERR_CNT_LIMIT[1:0] description

The fault error counter value is stored in the FLT_ERR_CNT[3:0] bits and starts at “0”

after a POR. The FLT_ERR_CNT[3:0] may be cleared in the application via I2C by writing

0b1 to the CLR_FLT_ERR_CNT bit and 0b0 to the NOT_CLR_FLT_ERR_CNT bit.

The FLT_ERR_CNT[3:0] decrements by '1' when the watchdog timer is refreshed after

the watchdog refresh counter reaches its maximum value.

Note: Use the CLR_FLT_ERR_CNT bit only if the watchdog is disabled. If watchdog is

enabled, use that to decrement the FLT_ERR_CNT[3:0]. Using the CLR_FLT_ERR_CNT

when watchdog is enabled is not recommended.

The fault error counter is incremented each time an assigned fault occurs.

OTP bit

Fault counter configuration

OTP_SW1_FLT_CNT_EN = 1

enables SW1 OV and/or UV faults to increment

FLT_ERR_CNT if the SW1 OV and/or UV faults are