MFS5600AMBA0ES datasheet(41/111 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

WD_WINDOW[3:0]

Watchdog window period

1110

512 ms

1111

1024 ms

Table 38. Watchdog window period configuration...continued

The duty cycle of the watchdog window is configurable from 31.25 % to 68.75 % with the

WDW_DC [2:0] bits. The new duty cycle is effective after the next watchdog refresh.

WDW_DC [2:0]

CLOSED window

OPEN window

000

31.25 %

68.75 %

001

37.5 %

62.5 %

010 (default)

50 %

011

62.5 %

37.5 %

100

68.75 %

31.25 %

Others

50 %

Table 39. Watchdog window duty cycle configuration

17.3.1 Simple watchdog

The simple watchdog uses a seed value that must be used to ‘pet’ the watchdog. The

MCU can send its own seed in WD_SEED register or use the default seed value 0x5AB2.

This seed must be written in the WD_ANSWER register during the OPEN watchdog

window.

When the result is right, the watchdog window is restarted. When the result is wrong,

a watchdog error counter is incremented and the watchdog window is restarted. See

Section 17.3.3 for watchdog error counter.

In case the watchdog answer from MCU is wrong, the “WD_BAD_DATA” bit is set to 1. In

case the watchdog answer (temporal domain) is wrong (timeout or refresh during closed

window), the “WD_BAD_TIMING” bit is set to 1.

In the simple watchdog configuration, it is not possible to write 0xFFFF and 0x0000 to the

WD_SEED register. A communication error (I2C_REQ_ERR = 1) is reported if writes of

0x0000 and 0xFFFF are attempted.

17.3.2 Challenger watchdog

The challenger watchdog is based on a question/answer process with the MCU. A 16-

bit pseudo-random word is generated by implementing a Linear Feedback Shift Register

(LFSR) in the FS5600. The MCU can send the seed of the LFSR or use the LFSR

generated by the FS600 and will perform a pre-defined calculation. The result should

be sent through I2C during the OPEN watchdog window and is verified by the FS5600.

When the result is right, the watchdog window is restarted and a new LFSR is generated.

When the result is wrong, the WD error counter is incremented, the watchdog window is

restarted and the LFSR value is not changed.

In case the watchdog answer from MCU is wrong, the “WD_BAD_DATA” bit is set to 1. In

case the watchdog answer (temporal domain) is wrong (timeout or refresh during closed

window), the “WD_BAD_TIMING” bit is set to 1.

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 2 August 2022

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