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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H753II датащи(PDF) 182 Page - STMicroelectronics |
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STM32H753II датащи(HTML) 182 Page - STMicroelectronics |
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182 / 361 page  Electrical characteristics (rev Y) STM32H753xI 182/360 DS12117 Rev 8 6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 99 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for DFSDMx). Table 99. DFSDM measured timing - 1.62-3.6 V(1) Symbol Parameter Conditions Min Typ Max Unit fDFSDMCLK DFSDM clock 1.62 V < VDD < 3.6 V - - 250 MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 V < VDD < 3.6 V -- 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V -- 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0] ≠0), 1.62 < VDD < 3.6 V -- 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0] ≠0), 2.7 < VDD < 3.6 V -- 20 (fDFSDMCLK/4) fCKOUT Output clock frequency 1.62 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.62 < VDD < 3.6 V Even division, CKOUTDIV[7:0] = 1, 3, 5... 45 50 55 % Odd division, CKOUTDIV[7:0] = 2, 4, 6... (((n/2+1)/(n+1))* 100)–5 (((n/2+1)/(n+1)) *100) (((n/2+1)/(n+1))* 100)+5 |
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