STM32H753II datasheet(26/361 Pages) STMICROELECTRONICS

26 / 361 page

Functional overview

STM32H753xI

26/360

DS12117 Rev 8

The boot loader is located in non-user System memory. It is used to reprogram the Flash

memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32

microcontroller System memory Boot mode application note (AN2606) for details.

3.5

Power supply management

3.5.1

Power supply scheme

STM32H53xI power supply voltages are the following:

•

VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD

pins.

•

VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE

•

VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and

OPAMP.

•

VDD33USB and VDD50USB:

VDD50USB can be supplied through the USB cable to generate the VDD33USB via the

USB internal regulator. This allows supporting a VDD supply different from 3.3 V.

The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.

•

VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.

•

VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,

1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and

ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the

following power domains that can be independently switch off.

–

D1 domain containing some peripherals and the Cortex®-M7 core.

–

D2 domain containing a large part of the peripherals.

–

D3 domain containing some peripherals and the system control.

During power-up and power-down phases, the following power sequence requirements

must be respected (see Figure 2):

•

When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must

remain below VDD + 300 mV.

•

When VDD is above 1 V, all power supplies are independent.

During the power-down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the microcontroller remains below 1 mJ. This allows external

decoupling capacitors to be discharged with different time constants during the power-down

transient phase.

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