LSM6DSV16X datasheet(33/196 Pages) STMICROELECTRONICS

33 / 196 page

6.6

Analog hub functionality

The LSM6DSV16X embeds an analog hub sensing functionality which is able to connect an analog input and

convert it to a digital signal for embedded processing.

In the LSM6DSV16X, the analog hub has a dedicated channel that can be activated by setting the AH_QVAR_EN

bit to 1 in the CTRL7 (16h) register.

The accelerometer sensor must be set in high-performance mode or in normal mode when the analog hub

channel is enabled.

The analog hub data-ready signal is represented by the AH_QVARDA bit of the STATUS_REG (1Eh) register.

This signal can be driven to the INT2 pin by setting the INT2_DRDY_AH_QVAR bit to 1 in the CTRL7 (16h)

Analog hub data are available as a 16-bit word in two’s complement in the AH_QVAR_OUT_L (3Ah) and

AH_QVAR_OUT_H (3Bh) registers at a fixed rate of 240 Hz (typical).

Analog signal data can be also processed by MLC/FSM logic.

The analog hub functionality is available in mode 1 connection mode for the I²C interface only. The external

analog lines have to be connected to pin 2 (SDx/AH1/Qvar1) and/or pin 3 (SCx/AH2/Qvar2), so the I²C-master

interface (mode 2) and the auxiliary SPI (mode 3) are not available when the analog hub is used.

The equivalent input impedance of the analog hub buffers can be selected by properly setting the

AH_QVAR_C_ZIN_[1:0] bits in the CTRL7 (16h) register.

6.7

Qvar functionality

The LSM6DSV16X embeds a Qvar sensor which is able to detect electric charge variations in the proximity of the

external electrodes connected to the device.

In the LSM6DSV16X, Qvar has a dedicated channel that can be activated by setting the AH_QVAR_EN bit to 1 in

the CTRL7 (16h) register.

The accelerometer sensor must be set in high-performance mode or in normal mode when the Qvar channel is

enabled.

The Qvar data-ready signal is represented by the AH_QVARDA bit of the STATUS_REG (1Eh) register. This

signal can be driven to the INT2 pin by setting the INT2_DRDY_AH_QVAR bit to 1 in the CTRL7 (16h) register.

Qvar data are available as a 16-bit word in two’s complement in the AH_QVAR_OUT_L (3Ah) and

AH_QVAR_OUT_H (3Bh) registers at a fixed rate of 240 Hz (typical).

Qvar data can also be processed by MLC/FSM logic.

The Qvar functionality is available in mode 1 connection mode for the I²C interface only. The external electrodes

have to be connected to pin 2 (SDx/AH1/Qvar1) and/or pin 3 (SCx/AH2/Qvar2), so the I²C-master interface (mode

2) and the auxiliary SPI (mode 3) are not available when Qvar is used.

The equivalent input impedance of the Qvar buffers can be selected by properly setting the

AH_QVAR_C_ZIN_[1:0] bits in the CTRL7 (16h) register.

6.8

Block diagram of filters

Figure 18. Block diagram of filters

ADC1

ADC2

Low-Pass

UI/EIS Gyro

Low-Pass

OIS Gyro

Low-Pass

OIS XL

Regs

array,

FIFO

interface

Interrupt

mng

Auxiliary

SPI

Voltage and current

references

Trimming circuit

and Test interface

Clock and phase

generator

Power

management

FTP

SCL/SPC

SDA/SDI/SDO

SDO/SA0

SPC_Aux

SDI_Aux

SDO_Aux

INT1

INT2

Low-Pass

UI XL

Gyro

UI/EIS/OIS

front-end

XL UI/OIS

front-end

Temperature

sensor

Regs

array

Interrupt

mng

I2C/

/SPI

MIPI I3C®

LSM6DSV16X

Analog hub functionality

DS13510 - Rev 1

page 33/196

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