L9961 datasheet(42/63 Pages) STMICROELECTRONICS

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The elementary WRITE operation consists of:

A START condition

The SLAVE ADDRESS byte (with R/ W = 0) identifying the slave device to be activated

The REGISTER ADDRESS byte identifying the memory address where data has to be written

Two data bytes

An optional CRC byte covering all the previous bytes.

In a block write, the operation can continue by sending other packets formed by two data bytes and an optional

CRC covering the previous two bytes. The REGISTER ADDRESS defined at step 3 will be considered as the

starting address, and the memory address counter will be incremented by 1 at every 2 bytes received.

In case REGISTER ADDRESS saturates, L9961 will generate a NACK and data will not be written into internal

regs.

In case the received CRC is wrong, L9961 generates a NACK and the corresponding data is not written into

internal registers.

The WRITE operation terminates with a STOP condition.

3.10.5

Electrical parameters

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

VB according operating range of Table 4; TJ according operating range of Table 7.

Table 31. I2C electrical parameters

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

FSCL

Communication frequency

Guaranteed by

design

400

kHz

tLOW

LOW period of the SCL clock

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

tHD_STA

SCL hold (high) time, after SDA falling edge has created

the START condition, for the START condition to be correctly

detected

0.6

μs

tSU_STA

SCL set-up time to high (SDA already high) before SDA falling

edge creates the START condition sequence (by falling when

SCL is steadily high)

0.6

μs

tHD_DAT

SDA hold time after SCL falling edge

300

tSU_DAT

SDA set-up time before SCL rising edge

100

Rise time of SDA signal

With 4.7 kΩ pullup

resistor and 40 pF

load

300

Fall time of SDA signal

With 4.7 kΩ pullup

resistor and 40 pF

load

300

trf_SCL

Rise/fall time SCL signal

300

tSU_STO

SCL set-up time to high (SDA already low) before SDA rising

edge creates the STOP condition sequence (by rising when SCL

is steadily high)

0.6

μs

tHD_STO

SCL hold (high) time, after SDA rising edge has created the

STOP condition, for the STOP condition to be correctly detected

0.6

μs

tBUF

Bus free time between a STOP and START condition

1.3

μs

Capacitive load for each bus line

400

tVD_DAT_ACK Data (ACK) valid time

0.9

μs

TI2C_TIMEOUT

L9961

I2C protocol layer

DS14012 - Rev 1

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