L9961 datasheet(17/63 Pages) STMICROELECTRONICS

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Fault

type

Assertion condition

IC reaction to

assertion

Release condition

IC reaction to flag

clear

Maskable

Cell

severe

If a cell voltage raises

above

VCELL_SEVERE_OV_

TH, the severe OV fault

is acknowledged

FAULTN_SAFE is

pulled low for

TFAULTN_SAFE_LOW (if

a pulse on

FAULTN_SAFE pin was

not already generated

after a previous not

masked and not cleared

Cell OV / Cell Severe

OV detection)

If a cell voltage falls

below

VCELL_SEVERE_OV_

TH, the cell severe OV

flag can be cleared by

MCU

FAULTN line is released

CELL_SEVERE_OV_R

ST_MSK masks

reaction FAULTN_SAFE

FAULTN line is asserted

CELL_SEVERE_OV_FA

ULTN_MSK masks

reaction on FAULTN pin

Cell

balance

If a cell

voltage falls below

VCELL_BAL_UV_TH,

the corresponding

Bal UV counter is

incremented by 1

The BAL<x>_UV flag is

set

If a cell

voltage raises above

VCELL_BAL_UV_TH,

the corresponding

Bal UV counter is

decremented by 1.

The Balancing FET

is restored to the

status defined by

the corresponding

BAL<x>_ON bit

VCELL<x>_EN

masks measurement

execution. The Bal UV

flag of a disabled cell

can always be cleared

If the Bal UV counter

reaches

VCELL_BAL_UV_CNT_

TH, it saturates the Bal

UV fault is

acknowledged

Any ongoing balancing

is stopped on the

affected cell, regardless

of BAL<x>_ON bit

If the Bal UV counter

reaches zero, the Bal

UV flag can be cleared

by MCU

FAULTN line is released

BAL_UV_BAL_MSK

masks reaction on

balancing

FAULTN line is asserted

BAL_UV_FAULTN_MSK

masks reaction on

FAULTN pin

3.4.1.1

Electrical parameters

All parameters are tested and guaranteed in the following conditions, unless otherwise noted:

VB according operating range of Table 4; TJ according operating range of Table 7.

Table 11. Cell voltage monitor electrical parameters

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VCELL_RANGE

Cell voltage input measurement range

Design info

4.7

VCELL_RES

Cell voltage measurement resolution

Design info, effective

range [0-5]V

1.22

(5 V/212)

NBIT

ADC bit number

Design info

bit

ICELL_LEAK

Cx leakage current

ADC not converting

500

VCELLERR1

ADC total conversion error

range 1

1 V ≤ VCELL < 1.5 V

-40 °C< TJ<120 °C

-25

VCELLERR2

ADC total conversion error

range 2

1.5 V ≤ VCELL ≤ 4.5 V

-40 °C< TJ<105 °C

-15

VCELLERR3

ADC total conversion error

range 3

4.5 V ≤ VCELL ≤ 4.7 V

-40 °C< TJ<120°C

-25

VCELLERR4

ADC total conversion error

range 4

1.5 V ≤ VCELL ≤ 4.5

105 °C < TJ < 120 °C

-25

VCELL_NOISE

Cell conversion noise

LSB rms

TCELL_FILTER1

Cell and VB acquisition filter time

0.8

L9961

Voltage conversion routine

DS14012 - Rev 1

page 17/63

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