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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COM90C66 датащи(PDF) 1 Page - SMSC Corporation |
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COM90C66 датащи(HTML) 1 Page - SMSC Corporation |
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1 / 76 page  1 COM90C66 Data Sheet with Erratas for Rev. B and Rev. D devices ARCNET ® ® Controller/Transceiver with AT ® ® Interface and On-Chip RAM FEATURES • ARCNET LAN Controller/Transceiver/ Support Logic/Dual-Port RAM • Integrates SMSC COM90C65 with 16-Bit Data Bus, Dual-Port RAM, and Enhanced Diagnostics Circuitry • Includes IBM® PC/AT® Bus Interface Circuitry • Supports 8- and 16-Bit Data Buses • Full 2K x 8 On-Chip Dual-Port Buffer RAM • Zero Wait State Arbitration for Most AT Buses • SMSC COM90C26 Software Compatible • Command Chaining Enhances Performance • Supports Memory Mapped and Sequential I/O Mapped Access to the Internal RAM Buffer • Compatible with the SMSC HYC9058/68/ 88 (COAX and Twisted Pair Drivers) • Token Passing Protocol with Self Reconfiguration Detection • Variable Data Length Packets • 16 Bits CRC Check/Generation • Includes Address Decoding Circuitry for On- Chip RAM, PROM and I/O • Supports up to 255 Nodes • Contains Software Accessible Node ID Register • Compatible with Various Topologies (Star, Tree, Bus, ...) • On-Board Crystal Oscillator and Reset Circuitry • Low Power CMOS, Single +5V Supply GENERAL DESCRIPTION The SMSC COM90C66 is a special purpose communications controller for interconnecting processors and intelligent peripherals using the ARCNET Local Area Network. The COM90C66 is unique in that it integrates the core ARCNET logic found in Standard Microsystems' original COM90C26 and COM90C32 with an on-chip 2K x 8 RAM, as well as the 16-bit data bus interface for the IBM PC/AT. Because of the inclusion of the RAM buffer in the COM90C66, a complete ARCNET node can be implemented with only one or two additional ICs (8- or 16-bit applications, respectively) and a media driver circuit. The ARCNET core remains functionally untouched, eliminating validation and compatibility concerns. The enhancements exist in the integration and the performance of the device. Maximum integration has been achieved by including the 2K x 8 RAM buffer on the chip, providing the immediate benefits of a lower device pin count and less board components. The performance is enhanced in four ways: a 16-bit data bus for operation with the IBM PC/AT; a zero wait state arbitration mechanism, due partly to the integration of the RAM buffer on- chip; the ability of the device to do consecutive transmissions and receptions via the Command Chaining operation; and improved diagnostics, allowing the user to control the system more efficiently. For most AT compatibles, the device handles zero wait state transfers. ARCNET is a registered trademark of Datapoint Corporation IBM, AT, PC/AT and Micro Channel are registered trademarks of International Business Machines Corporation |
Аналогичный номер детали - COM90C66 |
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Аналогичное описание - COM90C66 |
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