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COM90C66 датащи(PDF) 74 Page - SMSC Corporation

номер детали COM90C66
подробное описание детали  ARCNET Controller/Transceiver with AT Interface and On-Chip RAM
PDF  76 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM90C66 датащи(HTML) 74 Page - SMSC Corporation

Back Button COM90C66 Datasheet HTML 68Page - SMSC Corporation COM90C66 Datasheet HTML 69Page - SMSC Corporation COM90C66 Datasheet HTML 70Page - SMSC Corporation COM90C66 Datasheet HTML 71Page - SMSC Corporation COM90C66 Datasheet HTML 72Page - SMSC Corporation COM90C66 Datasheet HTML 73Page - SMSC Corporation COM90C66 Datasheet HTML 74Page - SMSC Corporation COM90C66 Datasheet HTML 75Page - SMSC Corporation COM90C66 Datasheet HTML 76Page - SMSC Corporation  
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74
FIGURE 18 - WRITE I/O CYCLE
Data Hold Time from IOW High
30
t1
t2
t3
t4
t5
Parameter
Address, nSBHE Set Up to BALE Low *
Address, nSBHE Hold after BALE Low *
Address, nSBHE, AEN Set Up to nIOW Low
Valid Data Set Up to nIOW High
min
20
20
25
typ
max
units
nS
nS
nS
nS
t6
9
nS
nIOW High to BALE High (Next Address)
30
nS
A2-A15, AEN Low to nIOCS16 Low
t7
0
25
nS
* For latched address, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode.
** 200 nS minimum inactive time on consecutive writes to the Data Register of the COM90C66.
Modified Version of Page 53 for Rev. D COM90C66 Only.
A0-A15,
VALID DATA
VALID
t2
t1
t3
t6
t7
BALE
nIOW
D0-D7 or
nTOPL
t4
AEN
nSBHE
D0-D15
nTOPH
nIOCS16
t5
**
t8
AEN Hold after nIOW High
10
t8
nS



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