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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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COM90C66 датащи(PDF) 72 Page - SMSC Corporation |
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COM90C66 датащи(HTML) 72 Page - SMSC Corporation |
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72 / 76 page  72 FIGURE 16 - WRITE RAM CYCLE A0-A19 VALID DATA VALID t2 t1 t3 BALE nMEMW D0-D7 nTOPL t4 nMEMCS16 nMEMCS16 (Unlatched) (Latched) t8 t9 t7 t5 t6 nSBHE D0-D15 or ** t2*** 30 t1 t2 t3 t4 t5 t6 Parameter Address, nSBHE Set Up to BALE Low * Address, nSBHE Hold after BALE Low * Address, nSBHE Set Up to nMEMW Low Valid Data Set Up to nMEMW High min 20 20 25 typ max units nS nS nS nS Data Hold Time from nMEMW High 9 nS nMEMW High to BALE High (Next Address) 30 nS A17-A19 to nMEMCS16 Low (Unlatched) (128K RAM Decode) A11-A19 to nMEMCS16 (Latched) (2K RAM Decode) 0 0 40 25 nS nS Address, nSBHE Invalid to nMEMCS16 High 0 nS t7 t8 t9 For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address Mode. 200nS minimum inactive time on consecutive memory writes to the COM90C66. * ** *** For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20 nsec after nMEMW Low. Modified Version of Page 51 for Rev. D COM90C66 Only. |
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