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COM90C66 датащи(PDF) 71 Page - SMSC Corporation

номер детали COM90C66
подробное описание детали  ARCNET Controller/Transceiver with AT Interface and On-Chip RAM
PDF  76 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM90C66 датащи(HTML) 71 Page - SMSC Corporation

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71
FIGURE 15 - READ RAM CYCLE
nMEMR High to nTOPH, nTOPL High
t1
t2
t3
t4
t5
t6
Parameter
Address, nSBHE Set Up to BALE Low *
Address, nSBHE Hold after BALE Low *
Address, nSBHE Set Up to nMEMR Low
nMEMR Low to Valid Data
nMEMR Low to nTOPH, nTOPL Low
min
20
20
25
0
0
typ
max
30
units
nS
nS
nS
nS
nS
nS
15
t7
nMEMR High to Data High Impedance
0
20
nS
t8
nMEMR High to BALE High (Next Address)
30
nS
A19-A17 to nMEMCS16 Low (Unlatched) (128K RAM Decode)
A19-A11 to nMEMCS16 Low (Latched) (2K RAM Decode)
Address, nSBHE invalid to nMEMCS16 High
t9
t10
t11
80
25
40
nS
nS
nS
0
0
0
A0-A19
VALID DATA
VALID
t2
t1
t3
t4
t5
t8
t9
t10
BALE
nMEMR
D0-D7
nTOPL
nTOPH,
nMEMCS16
(Unlatched)
nMEMCS16
(Latched)
D0-D15
or
nSBHE
t6
t7
t11
**
t2***
For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode
130ns minimum inactive time on consective memory reads from the COM90C66.
For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20nsec
after nMEMR Low.
*
**
***
Modified Version of Page 50 for Rev. D COM90C66 Only.



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