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XGS Family

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LANE MULTIPLEXING

The lane multiplexing function can be used to reduce the

number of output data lanes and thus the output data rate.

This can be useful in case the receiver cannot accept all 24

data lanes or the backend is unable to process the sensor’s

full data rate. The sensor has one multiplexer for each PHY;

six in total. Each multiplexer connects 4 datapath outputs to

one PHY and can be configured to distribute the data from

the 4 datapath inputs over either 1, 2, 3 or 4 outputs; i.e. the

sensor supports 4 multiplexing schemes:

• 4:4 multiplexing: no multiplexing; each datapath lane is

connected to a HiSPi lane (total of 24 lanes).

• 4:3 multiplexing: four datapath lanes are multiplexed to

three HiSPi lanes (total of 18 lanes).

• 4:2 multiplexing: four datapath lanes are multiplexed to

two HiSPi lanes (total of 12 lanes).

• 4:1 multiplexing: four datapath lanes are multiplexed to

a single HiSPi lane (total of 6 lanes).

The four different multiplexing schemes are illustrated in

Figures 27 to 30. The pixel readout order for each

multiplexing mode is depicted in Figures 31 to 34.

DP0(t0) … DP 0(t1)

DP1(t0) ... DP1(t1)

DP2(t0) ... DP2(t1)

DP3(t0) ... DP3(t1)

4:4

Multiplexer

DATAPATH_1

DATAPATH_0

time

DATAPATH_3

DATAPATH_2

DATA_0

DATA_1

DATA_2

DATA_3

4:3

Multiplexer

DATAPATH_1

DATAPATH_0

time

DATAPATH_3

DATAPATH_2

DATA_0

DATA_1

DATA_2

DP0(t0) … DP 3(t0)

DP1(t0) ... DP0(t1)

DP2(t0) ... DP1(t1)

4:2

Multiplexer

DATAPATH_1

DATAPATH_0

time

DATAPATH_3

DATAPATH_2

DATA_0

DATA_1

DP0(t0) … DP 2(t0)

DP1(t0) ... DP3(t0)

4:1

Multiplexer

DATAPATH_1

DATAPATH_0

time

DATAPATH_3

DATAPATH_2

DATA_0

DP0(t0) … DP 1(t0) ...

...DP2(t0) … DP 3(t0)

Figure 27. 4:4 Multiplexing (24 Lanes)

Figure 28. 4:3 Multiplexing (18 Lanes)

Figure 29. 4:2 Multiplexing (12 Lanes)

Figure 30. 4:1 Multiplexing (6 Lanes)

Table 12 lists the active data lanes in function of the

multiplexing scheme. As depicted in Table 12, HiSPi lane 0

is the lane that is always active, regardless of the selected

multiplex scheme.

Table 12. ACTIVE DATA LANES IN PHY0 IN FUNCTION OF MUX MODE

Mux Mode

Lane_0

Lane_2

Lane_4

Lane_6

4:4

4:3

4:2

4:1

NOTE: Lane usage is illustrated using the first four lanes only (i.e. for a single PHY).

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