XGS datasheet(23/53 Pages) ONSEMI

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XGS Family

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MASTER MODE (TRIGGERED)

Figure 17. Master Mode (Triggered)

In Triggered Master Mode, a rising edge on the

TRIG_INT pin is used to trigger the start of integration as

shown in Figure 17. The integration time is defined by

configuration

(integration_coarse,

integration_fine). The sensor shall autonomously integrate

during this predefined time, after which the EFOT operation

starts and the image array is read out sequentially. A falling

edge on the synchronization pin does not have any impact on

the readout or integration and subsequent frames are started

again for each rising edge.

Figure 18 below shows the pipelined operation in

triggered master mode (i.e. trigger assertion during frame

readout).

Figure 18. Integration Control in Triggered Master Mode

Note that each trigger reads out only one image.

The latency between a trigger event and the start of the

SFOT operation is constant and predictable. It is defined by

the coarse offset configuration + overhead.

NOTES:

• The trigger is an asynchronous signal which is

synchronized in the SCU. As a consequence,

synchronization jitter can be observed.

• The polarity of the TRIG_INT pin is controlled by

trig_int_polarity. The operation described above

corresponds to trig_int _polarity = ‘0’.

• The response time between a rising edge of TRIG_INT

and the start of integration is fixed, besides the

synchronization uncertainty and jitter.

• Changes in registers such as gain and integration_offset

can be configured to take effect in the same frame

(when uploaded before the raising edge of the trigger

signal) if gain_lat_comp or offset_lat_comp is disabled

or in the next frame (N+1 with readout in N+2) when

gain_lat_comp or offset_lat_comp is enabled. By

default, these registers are enabled in R0x3802.

• The following register is not used in this mode and has

no influence (implicitly defined by the trigger)

♦ frame_length

Minimum integration time limitations are listed in

Table 10.

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