STLC4420A datasheet(34/40 Pages) STMICROELECTRONICS

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Registers description

STLC4420A

34/40

HostRes

Host Reset flag - A logic 1 indicates that the previous

reset was generated by the Host asserting the HostReset

bit in this register.

SleepMode

SleepMode flag - A logic 1 indicates that the device is in

Sleep Mode, i.e. running off the low frequency oscillator.

(Read Only)

14:6

ClockDivisor

The clock divisor setting on the PMU clock control register

(Read Only)

Reserved

Not Implemented

UseSerHostOverRide

When asserted, SerHost mode is updated by bits 3:0

1 = Update SerHost mode based on bits 3:0

0 = No change to SerHost mode

Host_3_WireAdrDataWait

Number of wait states between Address and Data phase

in 3_Wire mode 0 = Zero wait states between Address

and Data phase in 3_Wire mode 1 = One wait state

between Address and Data phase in 3_Wire mode

Read value is currently selected 3_ WireAdrDataWait.

May be different that last written value when

UseSerHostOverRide is deasserted.

Host_3_WireMode

Select 3 wire mode using SPI_DIN for Serial data input

and output 0 = Use 4 wire mode, SPI_DIN input only and

SPI_DOUT output only 1 = Use 3 wire mode, SPI_DIN for

input and output

Read value is currently selected 3_ WireMode. May be

different that last written value when

UseSerHostOverRide is deasserted

Host_PhaseShift

Shift SPI_DIN and SPI_DOUT by 1 clock phase 0 = No

phase shift 1 = Phase shift SPI_DIN and SPI_DOUT by 1

clock phase

Read value is currently selected PhaseShift. May be

different that last written value when

UseSerHostOverRide is deasserted

Host_InvertClock

Select active edge of SPI_CLK 0 = Rising edge of

SPI_CLK is active edge

1 = Falling edge of SPI_CLK is active edge

Read value is currently selected InvertClock. May be

different that last written value when

UseSerHostOverRide is deasserted

Table 13.

Device control/status register

Bit number

Name

Description

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