STLC4420A datasheet(31/40 Pages) STMICROELECTRONICS

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STLC4420A

Registers description

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5.3

ARM interrupt enable

The ARM processor writes this register, and enables interrupts from the ARM interrupt

The format of the register is defined in Table 9.

5.4

Host interrupt register

The bits of this register reflect the Host interrupt register with the masking by the host

interrupt enable register. This register can be written or read while the device is in sleep

mode (for example, running off the low frequency oscillator) and not generate an

ARM_asleep interrupt.

The format of the register is defined in Table 10.

27:16

Reserved

Not Implemented

15:0

HOSTMSG

General purpose Host Message Interrupts. May be written by the

Host to cause an interrupt to the ARM processor.

Table 8.

ARM interrupt acknowledge (continued)

Bit position

Name

Description

Table 9.

ARM interrupt enable

Bit position

Name

Description

ARM_ASLEEP

Indicates that an access to hardware registers or device memory

(by Host) was attempted while the device was in sleep-mode.

DMA WR done

Last Write Occurred

DMA RD done

Last Read Occurred

DMA RD ready

DMA rd FIFO ready to be read

27:16

Reserved

Not Implemented

15:0

HOSTMSG

General purpose Host Message Interrupts. Written by the ARM

to enable Interrupt on selected bit(s)

Table 10.

Host interrupt register

Bit position

Name

Description

ARM_ASLEEP

Indicates that an access to hardware registers or device memory

(by Host) was attempted while the device was in sleep-mode.

DMA wr done

Last Write Occurred

DMA rd done

Last Read Occurred

DMA rd ready

DMA rd FIFO ready to be read

NotSleep

Not Implemented

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