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STLC4420A датащи(PDF) 25 Page - STMicroelectronics

номер детали STLC4420A
подробное описание детали  Single chip 802.11b/g/a WLAN radio
PDF  40 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STLC4420A датащи(HTML) 25 Page - STMicroelectronics

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STLC4420A
Serial host interface
25/40
The read data is registered on the 15 SPI_CLK of the address phase. SPI_CSX high time
must be 20ABClocks - 15SPI_CLKs. If ABClock period is 100ns (10 MHz) and SPI_CLK
period is 40ns then the time between writing DMA write address register and reading the
DMA data register is (20 * 100) - (15 * 40) = 1.4us. If the ABClock period is 25ns (40 MHz)
then SPI_CSX high time is < 0 for Read data to be valid. In this case, only the Min High time
for SPI_CSX must be observed.
4.4
Host registers
The Host can access the registers listed in Table 5.
Figure 17.
AHB bus timing
Table 5.
Host registers
Domain
A14-A8
Access
Sleep access
Description
Notes
SPI_CLK
X00 0000
X00 0010
RW
RW
ARM interrupt
(1), (2)
ARM
X00 0100
X00 0110
R--
ARM interrupt
enable
ARM
X00 1000
X00 1010
R
--
Host interrupt
(1)
SPI_CLK
X00 1100
X00 1110
RW
RW
Host interrupt
enable
SPI_CLK
X01 0000
X01 0010
W--
Host interrupt
acknowledge
Shared
X01 0100
X01 0110
RW
--
GP1
communication
Shared
X01 1000
X01 1010
RW
--
GP2
communication
Host
X10 0100
X10 0110
RW
RW
Device control/
status
(1), (2)
Host
X10 1000
RW
--
DMA data
Shared
X10 1100
RW
--
DMA write
control



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