WM8581 datasheet(52/94 Pages) WOLFSON

52 / 94 page

WM8581

Product Preview

PP Rev 1.0 March 2006

S/PDIF RECEIVE MODE CLOCKING

In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF

receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream. PLLB

must be configured to produce a specific reference clock frequency for the S/PDIF receiver.

The S/PDIF receiver has four clocking modes based on the incoming S/PDIF stream sample rate. The

modes are:

•

Mode 1: Incoming S/PDIF Sample Rate = 192kHz +/- 1%

•

Mode 2: Incoming S/PDIF Sample Rate = 88.2kHz -1% to 96kHz +1%

•

Mode 3: Incoming S/PDIF Sample Rate = 44.1kHz -1% to 48kHz +1%

•

Mode 4: Incoming S/PDIF Sample Rate = 32kHz +/- 1%

Before the S/PDIF receiver is enabled, it is important that the PLLB_N and PLLB_K register values (and the

PRESCALE_x values as appropriate) are manually configured in a specific default state. The PLLB_N and

PLLB_K register values (and the PRESCALE_x values as appropriate) must also be manually re-configured

when a change of the clocking mode is detected and the change is to mode 1 or from mode 1. Note that the

PRESCALE_A value must always be set to the same value as PRESCALE_B.

The specified PLLB f2 frequencies that must be configured using the PLLB_N and PLLB_K register values

(and the PRESCALE_x values as appropriate) for reception of specific S/PDIF sample rates are as follows:

•

Mode 1 (192kHz Sample Rate): PLLB f2 = 98.304MHz

•

Modes 2/3/4 (32/44.1/48/88.2/96kHz Sample Rates): PLLB f2 = 94.3104MHz

The FREQMODE_B[1:0] bits and POSTSCALE_B bit are not used in PLL S/PDIF recever mode.

The PLL register settings are configured by default to allow 32/44.1/48/88.2/96kHz (modes 2/3/4) sample

rate S/PDIF receiver operation using a 12MHz crystal clock. The appropriate PLLB register values must be

updated if:

•

Any crystal clock frequency other than 12MHz is used.

•

A S/PDIF stream with 192kHz sample rate (mode 1) is detected.

In either case, reprogramming of the PLLB_N and PLLB_K values (and the PRESCALE_x values as

appropriate) is necessary.

Refer to Table 46 for details of a number of recommended PLLB configurations. Many other configurations

are possible; please refer to PLL Configuration section for details regarding how to calculate alternative

settings.

OSC

CLK

(MHz)

PRE-

SCALE_X

S/PDIF RECEIVER

SAMPLE RATE(S) (kHz)

(MHz)

PLLB_N

(Hex)

PLLB_K

(Hex)

COMMENT

11.2896

32 / 44.1 / 48 / 88.2 / 96

11.2896 94.3104 8.3537

16A3B3

Set N, K

11.2896

192

11.2896

98.304

8.7075

2D4766

Set N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Default Setting

192

98.304

8.192

C49BA

Set N, K

12.288

32 / 44.1 / 48 / 88.2 / 96

12.288

94.3104

7.675

2B3333

Set K

12.288

192

12.288

98.304

Set N, K

19.2

32 / 44.1 / 48 / 88.2 / 96

9.6

94.3104

9.824

346C6A

Set Prescales, N, K

19.2

192

9.6

98.304

10.24

F5C28

Set Prescales, N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Set Prescales

192

98.304

8.192

C49BA

Set Prescales, N, K

32 / 44.1 / 48 / 88.2 / 96

13.5

94.3104

6.986

3F19E5

Set Prescales, N, K

192

13.5

98.304

7.2818

1208A5

Set Prescales, K

Table 46 S/PDIF Receive Mode PLLB Initial Configuration Examples

WM8581 датащи(PDF) 52 Page - Wolfson Microelectronics plc

WM8581 датащи(HTML) 52 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

датащи скачать

ссылки URL