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WM8581 датащи(PDF) 41 Page - Wolfson Microelectronics plc

номер детали WM8581
подробное описание детали  Multichannel CODEC with S/PDIF Transceiver
PDF  94 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8581 датащи(HTML) 41 Page - Wolfson Microelectronics plc

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WM8581
w
PP Rev 1.0 March 2006
41
ADC INTERFACE
The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or
ADCMCLK. However, if the S/PDIF receiver is powered up, the PLLACLK and PLLBCLK are invalid
for ADC operation, so the choice is limited to ADCMCLK (default) or MCLK. The rate that the ADC
operates at is determined by the ADC Rate module. It calculates the rate based on the digital routing
setup. If the ADC is sourced by the PAIF Transmitter, PAIFTX_LRCLK is used in the rate calculation.
If the ADC is sourced by the SAIF Transmitter (and PAIF Transmitter has another source),
SAIF_LRCLK is used in the rate calculation. If the S/PDIF Transmitter (only) is sourcing the ADC,
then the rate is set by the ADC_RATE register bits.
Figure 26 ADC Clock Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8
3:2
ADC_CLKSEL
00
ADC clock source
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
R29
7:5
ADCRATE[2:0]
010
ADC Rate Control (only used when
the S/PDIF Tx is the only interface
sourcing the ADC)
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
Table 33 ADC Clock Control



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