AD5413 datasheet(30/49 Pages) AD

30 / 49 page

AD5413

Data Sheet

Rev. 0 | Page 30 of 49

Sticky Diagnostic Results Bits section for more details). Therefore,

to clear the SPI_CRC_ERR bit, write a 1 to Bit 0 of the

DIGITAL_DIAG_RESULTS register. Writing a 1 clears the

SPI_CRC_ERR bit and causes the FAULT pin to return high,

assuming that there are no other active faults. When configuring

the FAULT_PIN_CONFIG register, the user decides whether the

SPI CRC error affects the FAULT pin. See the FAULT Pin

Configuration Register section for more details. The SPI CRC

feature is used for both transmitting and receiving data packets.

SPI Interface Slip Bit

An additional slip bit enhances the interface robustness. The MSB

of the SPI frame must equal the inverse of MSB – 1 for the frame to

be considered valid. If an incorrect slip bit is detected, the data is

ignored and the SLIPBIT_ERR bit in the DIGITAL_DIAG_

RESULTS register is asserted.

SPI Interface SCLK Count Feature

An SCLK count feature is also built into the SPI diagnostics. If the

CRC is enabled, only SPI frames with exactly 32 SCLK falling edges

are accepted by the interface as a valid write. If the CRC is disabled,

SPI fames with either 24 or 32 SCLK falling edges are accepted by

the interface as a valid write. SPI frame lengths other than these

are ignored and the SCLK_COUNT_ERR flag asserts in the

DIGITAL_DIAG_RESULTS register.

Readback Modes

The AD5413 offers the following four readback modes:



Two-stage readback mode



Autostatus readback mode



Shared SYNC autostatus readback mode



Echo mode

The two-stage readback consists of a write to a dedicated

operation (NOP) command, during which the contents of the

selected register are available on the SDO pin.

Table 11. SDO Contents for Read Operation

MSB

LSB

[D31:D30] D29

[D28:24]

[D23:D8]

[D7:D0]

0b10

FAULT

status

address

Data

CRC

Bits[D31:D30] = 0b10 are used for synchronization purposes

during readback.

If autostatus readback mode is selected, the status register contents

are available on the SDO line during each SPI transaction. This

feature allows the user to continuously monitor the status register

and to act quickly if a fault occurs. The AD5413 powers up with

this feature disabled. When this feature is enabled, the normal

two-stage readback feature is not available. Only the status register

is available on the SDO when autostatus readback mode is

selected. To read back other registers, disable the automatic

readback feature and then follow the two-stage readback

sequence. The automatic status readback can be re-enabled

after the register is read back.

The shared AD5413 SYNC autostatus readback is a unique

version of the autostatus readback mode used to avoid SDO bus

contention when multiple devices share the same SYNC line. See

the Shared Autostatus Readback Mode section for more details.

Echo mode behaves similarly to autostatus readback mode, except

that every second readback consists of an echo of the previous

command written to the AD5413 (see Figure 63). See the Reading

from Registers section for further details on the readback modes.

COMMAND

STATUS REGISTER

CONTENTS

Figure 63. SDO Contents in Echo Mode

USER DIGITAL OFFSET AND GAIN CONTROL

The AD5413 has a USER_GAIN register and a USER_OFFSET

chain. The USER_GAIN register allows the user to adjust the DAC

channel gain in steps of 1 LSB. The USER_GAIN register coding is

straight binary, as shown in Table 12. The default code in the

USER_GAIN register is 0xFFFC, which results in a no gain factor

applied to the programmed output. In theory, the gain can be

tuned across the full range of the output. In practice, the

maximum recommended gain trim is approximately 50% of the

programmed range to maintain accuracy. The lower two bits,

D1 and D0, are unused and must not be written to.

Table 12. Gain Register Adjustment

Gain Adjustment Factor

D13

[D12:D3]

[D1:D0]

16383/16384

…

2/16384

1/16384

The USER_OFFSET register allows the user to adjust the DAC

channel offset from −8192 LSBs to +8192 LSBs in steps of 1 LSB.

The USER_OFFSET register coding is straight binary, as shown

in Table 13. The default code in the USER_OFFSET register is

0x8000, which results in zero offset programmed to the output.

The lower two bits, D1 and D0, are unused and must not be

written to.

Table 13. Offset Register Adjustment

Gain Adjustment Factor

D13

[D12:D3]

[D1:D0]

+8192 LSBs

+8191LSBs

…

No Adjustment (Default)

…

−8191 LSBs

−8192 LSBs

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