AD5413 datasheet(32/49 Pages) AD

32 / 49 page

AD5413

Data Sheet

Rev. 0 | Page 32 of 49

SOFTWARE RESET

A software reset requires two consecutive writes of 0x15FA and

0xAF51, respectively, to the key register. A device reset can be

initiated via the hardware RESET pin or the software reset keys.

The RESET_OCCURRED bit in the DIGITAL_DIAG_RESULTS

power-up. Both diagnostic results registers implement a write of 1

to clear the function. That is, write a 1 to this bit to clear the bit (see

the Sticky Diagnostic Results Bits section).

CALIBRATION MEMORY CRC

For each calibration memory refresh cycle, which is either

initiated via a key code write to the key register or automatically

initiated when the RANGE bits (Bits[3:0]) of the DAC_CONFIG

contents of the calibration memory shadow registers. The result

of this CRC is compared with the factory stored reference CRC

value. If the CRC values match, the read of the entire calibration

memory is considered valid. If the values do not match, the CAL_

MEM_CRC_ERR bit in the DIGITAL_DIAG_RESULTS register

is set to 1. This calibration memory CRC feature is enabled by

default. Disable this feature via the CAL_MEM_CRC_EN bit in

the DIGITAL_DIAG_CONFIG register.

Two-stage readback commands are permitted while this

calibration memory refresh cycle is active. However, a write to

any register other than the TWO_STAGE_READBACK_SELECT

ERR bit in the DIGITAL_DIAG_RESULTS register. As described

in the Programming Sequence to Enable the Output section, a

wait period of 500 μs is recommended after a calibration memory

refresh cycle is initiated.

INTERNAL OSCILLATOR DIAGNOSTICS

An internal frequency monitor uses the internal oscillator (MCLK)

to increment a 16-bit counter at a rate of 1 kHz (MCLK/10000).

The counter value can be read in the FREQ_MONITOR register.

The user can poll this register periodically and use the result as a

diagnostic tool for MCLK (to monitor that the oscillator is

running) and to measure the oscillator frequency. This counter

feature is enabled by default via the FREQ_MON_EN bit in the

DIGITAL_DIAG_CONFIG register.

If the MCLK oscillator stops, the AD5413 sends a specific code

of 0x07DEAD to the SDO line for each SPI frame. This oscillator

dead code feature is enabled by default. To disable this feature,

clear the OSC_STOP_DETECT_EN bit in the GP_CONFIG1

timing specifications described in Table 3.

STICKY DIAGNOSTIC RESULTS BITS

The AD5413 contains a digital diagnostic results register

(DIGITAL_DIAG_RESULTS) and an analog diagnostic results

respectively, for the diagnostic error bits). The diagnostic results

bits contained within these registers are sticky and a 1 must be

written to each bit to clear the error bit (R/W-1-C). If the fault is

still present after writing a 1 to the bit in question, the error bit

does not clear to 0. When Logic 1 is written to the bit, the bit

updates to the latest value, which is Logic 1 if the fault is still

present, and Logic 0 if the fault is no longer present.

There are two exceptions to this R/W-1-C access within the

DIGITAL_DIAG_RESULTS register, the CAL_MEM_

UNREFRESHED bit and the SLEW_BUSY bit, which

automatically clear when the calibration memory refreshes

and when the output slew completes, respectively.

The STATUS register contains a DIG_DIAG_STATUS bit and an

ANA_DIAG_STATUS bit. Both bits are the result of a logical OR

of the diagnostic results bits contained in each diagnostic results

OR of the ANA_DIAG_STATUS bit, and all digital diagnostic

flag bits, except for the SLEW_BUSY bit, are included in the logical

OR of the DIG_DIAG_STATUS bit. The OR’ed bits within the

status register are read only and are not sticky (R/W-1-C).

BACKGROUND SUPPLY AND TEMPERATURE

MONITORING

Excessive die temperature and overvoltage are related to

common cause failures.

The die has a built in temperature sensor with a ±5°C accuracy.

The die temperature is monitored by a comparator and the

background temperature comparators are permanently enabled.

Programmable trip points corresponding to 142°C, 127°C, 112°C,

and 97°C can be configured in the GP_CONFIG1 register. If the

temperature of the die exceeds the programmed limit, the relevant

status bit in the ANALOG_DIAG_RESULTS register is set, and

the FAULT pin asserts low.

The low voltage supplies on the AD5413 are monitored via low

power static comparators. This monitoring function is disabled

by default and is enabled via the COMPARATOR_CONFIG bits

in the GP_CONFIG2 register. The INT_EN bit in the DAC_

CONFIG register must be set for the REFIN buffer to be powered

up and for this node to be available to the REFIN comparator. The

monitored nodes are REFIN, REFOUT, VLDO, and an internally

generated AVCC voltage. A status bit in the ANALOG_DIAG_

RESULTS register corresponds to each monitored node. If any

monitored node supplies exceed the upper or lower threshold

values (see Table 14 for the threshold values), the corresponding

status bit is set. Note that if a REFOUT fault occurs, the

REFOUT_ERR status bit is set. The INT_AVCC, VLDO, and

temperature comparator status bits (DIE_TEMP_ERR) can then

also be set because REFOUT is used as the comparison voltage

for these nodes.

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