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Data Sheet

AD5413

Rev. 0 | Page 29 of 49

DEVICE FEATURES AND DIAGNOSTICS

DIGITAL SLEW RATE CONTROL

The AD5413 slew rate control feature allows the user to control

the rate at which the output value changes. This feature is available

in both current mode and voltage mode. Disabling the slew rate

control feature changes the output value at a rate limited by the

output drive circuitry and the attached load. To reduce the slew

rate, enable the slew rate control feature to cause the output to

digitally step from one output value to the next at a rate defined by

two parameters that are accessible via the DAC_CONFIG register.

These two parameters are SR_CLOCK and SR_STEP. The

SR_CLOCK parameter defines the rate at which the digital slew is

updated. For example, if the selected update rate is 8 kHz, the

output updates every 125 μs. In conjunction with the SR_CLOCK

parameter, the SR_STEP parameter defines how much the output

value changes at each update. Together, both parameters define the

rate of change of the output value. The following equation

describes the slew rate as a function of the step size, the slew rate

frequency, and the LSB size:

Output Change

Slew Time

tep Size Slew Rate Frequency LSB Size





where:

Slew Time is expressed in seconds.

Output Change is expressed in amps for current output mode

or volts for voltage output mode

Step Size is the step size in amps for current output mode, or

volts for voltage output mode

Slew Rate Frequency is the SR_CLOCK parameter value.

LSB Size is the SR_STEP parameter value.

When the slew rate control feature is enabled, all output

changes occur at the programmed slew rate.

AD5413 ADDRESS PINS

The AD5413 address pins (AD0 and AD1) are used in conjunction

with the AD5413 address bits within the SPI frame (see Table 10)

to determine which AD5413 device is being addressed by the

system controller. Up to four devices can be independently

addressed on one board using the two address pins.

SPI INTERFACE AND DIAGNOSTICS

The AD5413 is controlled over a 4-wire SPI with an 8-bit cyclic

redundancy check (CRC-8) that is enabled by default. The input

shift register is 32 bits wide and data is loaded into the device

MSB first under the control of the SCLK signal. Data is clocked

in on the falling edge of SCLK. If CRC is disabled, the SPI is

reduced to 24 bits. A 32-bit frame is still accepted, but the last 8

bits are ignored.

Table 10. Writing to a Register (CRC Enabled)

MSB

LSB

D31

[D30:D29]

[D28:D24]

[D23:D8]

[D7:D0]

Slip bit

AD5413 address

Data

CRC

As shown in Table 10, every SPI frame contains two AD5413

address bits. These bits must match the AD0 pin and AD1 pin

for a particular device to accept the SPI frame on the bus.

SPI Cyclic Redundancy Check

To verify that data is correctly received in noisy environments, the

AD5413 offers a CRC based on a CRC-8. The device controlling

the AD5413, either a micro gate array or a field-programmable

gate array (FPGA), generates an 8-bit frame check sequence using

the following polynomial:

C(x) = x8 + x2 + x1 + 1

This 8-bit frame check sequence is added to the end of the

data-word and 32 bits are sent to the AD5413 before pulling

SYNC high (see Figure 62).

SDI

SYNC

SCLK

UPDATE ON SYNC HIGH

MSB

D23

LSB

24-BIT DATA

24-BIT DATA TRANSFER, NO CRC ERROR CHECKING

SDI

FAULT

SYNC

SCLK

UPDATE ON SYNC HIGH

ONLY IF ERROR CHECK PASSED

FAULT PIN GOES LOW

IF ERROR CHECK FAILS

MSB

D31

LSB

24-BIT DATA

8-BIT CRC

32-BIT DATA TRANSFER WITH CRC ERROR CHECKING

Figure 62. CRC Timing (Assume LDAC = 0)

If the SPI_CRC_EN bit in the DIGITAL_DIAG_CONFIG register

is set high (default state), supply a frame that is exactly 32 bits

wide and contains the 24 data bits and the 8-bit CRC. If the

CRC check is valid, the data is written to the selected register.

If the CRC check fails, the data is ignored, the FAULT pin goes

low, and the FAULT pin status bit and the digital diagnostic

status bit (DIG_DIAG_STATUS) in the status register are asserted.

A subsequent readback of the DIGITAL_DIAG_RESULTS register

shows that the SPI_CRC_ERR bit is also set. This register is per

individual bits. A write one per bit clears the register (see the

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