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PCF8545 датащи(PDF) 10 Page - NXP Semiconductors |
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PCF8545 датащи(HTML) 10 Page - NXP Semiconductors |
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10 / 68 page ![]() NXP Semiconductors PCF8545 Universal LCD driver for multiplex rates up to 1:8 Effect of setting PD Effect on function Mode settings 0 1 backplane output E = 1 normal function VSS segment output E = 1 normal function VSS internal oscillator OSC = 0, COE = 1 on off OSCCLK pin OSC = 0, COE = 1 output of internal oscillator frequency VDD OSCCLK pin OSC = 1 input clock clock input, can be logic 0, logic 1, or left floating Table 8. Effect of the power-down bit (PD) With the following sequence, the PCF8545 can be set to a state of minimum power consumption, called power-down mode. START Disable display by setting bit E logic 0 External clock can be removed now 013aaa447 Enable power- down mode with PD = 1 STOP Figure 6. Recommended power-down sequence Remarks: • It is necessary to run the power-down sequence before removing the supplies. Depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (see Section 9). Otherwise it may cause unwanted display artifacts. If an uncontrolled removal of the supply happens, the PCF8545 does not get damaged. • Static voltages across the liquid crystal display can build up when the external LCD supply voltage (VLCD) is on while the IC supply voltage is off, or the other way around. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. • A clock signal must always be supplied to the device when the display is active. Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. First disable the display and afterwards remove the clock signal. PCF8545 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 2 — 4 October 2021 10 / 68 |
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