MF4SAM3 datasheet(19/31 Pages) NXP

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NXP Semiconductors

MF4SAM3

MIFARE SAM AV3 secure access module

MF4SAM3

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Product short data sheet

Rev. 3.0 — 2 August 2019

COMPANY PUBLIC

561930

19 / 31

[2]

At minimum IOx input signal HIGH or LOW level voltage pulse width of 3.2 µs. This timing specification applies to ISO7816 configurations down to a

minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.

[3]

At minimum IOx input signal HIGH or LOW level voltage pulse width of less than 3.2 µs. This timing specification applies to ISO7816 configurations

beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/

Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 µs, and in a time of 400 ns for trIO_max and tfIO_max,

matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.

[4]

ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal. A ± 15 % tolerance range

yields the allowed limits of 0.85 MHz and 11.5 MHz.

[5]

During AC testing the inputs CLK, RST_N, IO1, IO2 and IO3 are driven at 0 V to +0.3 V for a LOW input level and at VDD - 0.3 V to VDD for a HIGH input

level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD (see Figure 9).

[6]

The maximum CLK rise and fall time is 10% of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the

maximum allowed CLK rise and fall time is 50 ns, if 10% of the CLK period is shorter than 50 ns.

[7]

The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.

Figure 9. External clock drive and AC test timing reference points of CLK, RST_N, IO1, IO2 and IO3 (see [1] and [2])

[1]

During AC testing the inputs CLK, RST_N, IO1, IO2 and IO3 are driven at 0 V to +0.3 V for a LOW input level and at VDD - 0.3 V to VDD for a HIGH input

level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD.

[2]

tr is defined as rise time between 10% and 90% of the signal amplitude.

tf is defined as fall time between 90% and 10% of the signal amplitude.

Table 11. Electrical AC characteristics of TP1 and TP2

Conditions: (A) VDD = 1.62 to 1.98 V: VDDAE = VDD; (B) VDD = 2.2 to 5.5 V (i.e. outside Class C supply range):

VDDAE(nom) = 1.8 V; VSS = 0 V; Tamb = -25 °C to +85 °C, unless otherwise specified

Symbol Parameter

Conditions

Min

Typ

Max

Unit

trTP

TP input rise time

Input/reception mode

μs

tfTP

TP input fall time

Input/reception mode

μs

trOTP

TP output rise time

Output/transmission mode;

C_L = 30 pF

tfOTP

TP output fall time

Output/transmission mode;

C_L = 30 pF

CiTP

Pin characteristics TP1, TP2

Test frequency = 1 MHz;

Tamb = -25 °C

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