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MF4SAM3 датащи(PDF) 18 Page - NXP Semiconductors |
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MF4SAM3 датащи(HTML) 18 Page - NXP Semiconductors |
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18 / 31 page ![]() NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module MF4SAM3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 18 / 31 9 Dynamic characteristics Remark: The P6022y VB only supports one single IO1. 9.1 General, ISO/IEC 7816 I/O and ISO/IEC 14443 I/O interfaces Table 10. Electrical AC characteristics of IO1, IO2, IO3, CLK and RST_N Conditions: VDD = 1.62 V to 5.5 V; VSS = 0 V; Tamb = -25°C to +85 °C, unless otherwise specified Symbol Parameter Conditions Min Typ[1] Max Unit Input/Output: IO1, IO2 and IO3 [2] - - 1 μs trIO I/O Input rise time Input/reception mode [3] - - 0.25 × tIOWx_min μs [2] - - 1 μs tfIO I/O Input fall time Input/reception mode [3] - - 0.25 × tIOWx_min μs trOIO I/O Output rise time Output/transmission mode; CL = 30 pF - - 0.1 μs tfOIO I/O Output fall time Output/transmission mode; CL = 30 pF - - 0.1 μs Inputs: CLK and RST_N fCLK External clock frequency in ISO/IEC 7816 UART applications tCLKW, Tamb and VDD in their spec'd limits [4] 0.85 - 11.5 MHz tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) [5] 40 - 60 % trCLK CLK input rise time [6] - - see [6] tfCLK CLK input fall time [6] - - see [6] trRST RST_N input rise time [7] - - 400 μs tfRST RST_N input fall time [7] - - 400 μs tRW Reset pulse width (RST_N low) 40 - - μs tWKP Wake-up time from SLEEP mode fCLKmin ≤ fCLK ≤ fCLKmax - 17 20 μs level triggered ext.int. - 20 - μs tWKPIO I/Ox LOW time for wake-up from SLEEP mode edge triggered ext.int. - 20 - μs tWKPRST RST_N LOW time for wake-up from SLEEP mode 40 - - μs Inputs: CLK, RST_N, IO1, IO2, IO3 CPIN Pin capacitances CLK, RST_N, IO1, IO2, IO3 Test frequency = 1 MHz; Tamb = 25 °C - - 10 pF [1] Typical values are only referenced for information. They are subject to change without notice. |
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