STM32WL55JC datasheet(43/147 Pages) STMICROELECTRONICS

43 / 147 page

DS13293 Rev 2

43/147

STM32WL55/54xx

Functional overview

•

DMA capability for either DAC channel

•

triggering with timer events, synchronized with DMA

•

triggering with external events

Sample-and-hold low-power mode, with internal or external capacitor

3.22

Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for

ADC, and also as voltage reference for external components through the VREF+ pin.

VREFBUF supports two voltages: 2.048 V and 2.5 V.

An external voltage reference can be provided through the VREF+ pin when VREFBUF

is off.

3.23

Comparator (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage

(internal or external), hysteresis and speed (low speed for low-power) and with selectable

output polarity.

The reference voltage can be one of the following:

•

external I/O

•

internal reference voltage or submultiple (1/4, 1/2, 3/4)

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,

and can be also combined into a window comparator.

3.24

True random number generator (RNG)

The devices embed a true RNG that delivers 32-bit random numbers generated by an

integrated analog circuitry.

The RNG is a true random number generator that provides full entropy outputs to the

application as 32-bit samples. It is composed of a live entropy source (analog) and an

internal conditioning component.

3.25

Advanced encryption standard hardware accelerator (AES)

The AES encrypts or decrypts data, using an algorithm and implementation fully compliant

with the advanced encryption standard (AES) defined in FIPS (federal information

processing standards) publication 197.

Multiple chaining modes are supported (ECB, CBC, CTR, GCM, GMAC, CCM), for key

sizes of 128 or 256 bits. The AES supports DMA single transfers for incoming and outgoing

data (two DMA channels required).

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