STM32WL55JC datasheet(16/147 Pages) STMICROELECTRONICS

16 / 147 page

Functional overview

STM32WL55/54xx

16/147

DS13293 Rev 2

performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 48 MHz.

3.4

Memory protection unit (MPU)

The memory protection unit (MPU) is used to manage the CPU1 and CPU2 accesses to

memory, to prevent one task to accidentally corrupt the memory or resources used by any

other active task. This memory area is organized into up to eight protected areas that can in

turn be divided up into eight subareas. The protection area sizes are between 32 bytes and

the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5

Memories

3.5.1

Embedded Flash memory

The Flash memory interface manages the accesses from CPU1 AHB ICode/DCode and

CPU2 AHB Sbus to the Flash memory. It implements the access, the erase and program

Flash memory operations, and the read and write protection.

The main features of the Flash memory are listed below:

•

Memory organization: 1 bank

–

main memory: up to 256 Kbytes

–

page size: 2 Kbytes

•

72-bit wide data read (64 bits plus 8 ECC bits)

•

72-bit wide data write (64 bits plus 8 ECC bits)

•

Page erase and mass erase

Flexible protections can be configured thanks to option bytes:

•

Readout protection (RDP) to protect the whole memory. Three levels are available:

–

Level 0: no readout protection

–

Level 1: memory readout protection. The Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is

selected.

–

Level 2: chip readout protection. Debug features (JTAG and serial wire), boot in

SRAM and bootloader selection are disabled (JTAG fuse). This selection can only

be reverted by the secure CPU2.

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