STM32WL55JC datasheet(49/147 Pages) STMICROELECTRONICS

49 / 147 page

DS13293 Rev 2

49/147

STM32WL55/54xx

Functional overview

3.32

Serial peripheral interface (SPI)/integrated-interchip sound

interface (I2S)

The SPI/I2S interface can be used to communicate with external devices using the SPI

protocol or the I2S audio protocol. SPI or I2S mode is selectable by software. SPI Motorola®

mode is selected by default after a device reset.

The SPI protocol supports half-duplex, full-duplex and simplex synchronous, serial

communication with external devices. The SPI interface can be configured as master and, in

this case, it provides the communication clock (SCK) to the external slave device. The SPI

interface can also operate in multimaster configuration.

The I2S protocol is also a synchronous serial communication interface. It can operate in

slave or master mode with half-duplex communication. It can address four different audio

standards including the Philips I2S standard, the MSB- and LSB-justified standards and the

PCM standard.

Dual clock domain and wakeup from low-power mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver enable

USART data length

7, 8 and 9 bits

Tx/Rx FIFO

Tx/Rx FIFO size

1. X = supported.

Table 16. USART/LPUART features (continued)

USART modes/features(1)

USART1/2

LPUART1

Table 17. SPI and SPI/I2S implementation(1)

1. The SPI1 and SPI2S2 instances are general purpose type while the SUBGHZSPI instance is dedicated for

Sub-GHz radio control exclusively. Radio is controlled internally through SUBGHZSPI and, for debug

purpose only, from the external.

Features

SPI1

SPI2S2

SUBGHZSPI

Enhanced NSSP and TI modes

Yes

Hardware CRC calculation

Yes

I2S support

Yes

Data size configurable (bits)

from 4 to 16

Rx/Tx FIFO size (bits)

Wakeup capability from LPSleep

Yes

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