STM32WL55JC datasheet(15/147 Pages) STMICROELECTRONICS

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DS13293 Rev 2

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STM32WL55/54xx

Functional overview

3.1

Architecture

The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller

subsystem using an Arm Cortex-M4 (called CPU1) and an Arm Cortex-M0+ (called CPU2).

An RF low-layer stack is needed and is to be run on CPU1 or CPU2, whereas the host

application code is preferably run on CPU1.

The RF subsystem communication is done through an internal SPI interface.

All secure code must be run by CPU2.

3.2

Arm Cortex-M cores

With its embedded Arm cores, the STM32WL55/54xx devices are compatible with all

Arm tools and software.

Figure 1 shows the general block diagram of the STM32WL55/54xx devices.

Arm Cortex-M4

The Arm Cortex-M4 is a processor for embedded systems. It has been developed to provide

a low-cost platform that meets the needs of MCU implementation, with a reduced pin count

and low-power consumption, while delivering outstanding computational performance and

an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering

the high-performance expected from an Arm core in the memory size usually associated

with 8- and 16-bit devices.

This processor supports a set of DSP instructions that allow efficient signal processing and

complex algorithm execution.

Arm Cortex-M0+

The Arm Cortex-M0+ is an entry-level processor for embedded systems. It has been

developed to provide lowest power consumption in the Cortex-M family, while delivering

good computation performance and response to interrupts.

The Arm Cortex-M0+ 32-bit RISC processor features good code-efficiency with ultra-low

power consumption in the memory size usually associated with 8-bit and 16-bit devices.

3.3

Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator that is optimized for STM32 industry-standard

Arm Cortex-M4 processor. The ART Accelerator balances the inherent performance

advantage of the Arm Cortex-M4 over Flash memory technologies, that normally require the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 60 DMIPS performance at 48 MHz, the ART Accelerator

implements an instruction prefetch queue and branch cache, that increases the program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

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