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STM32WL55JC датащи(PDF) 131 Page - STMicroelectronics

номер детали STM32WL55JC
подробное описание детали  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
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производитель  STMICROELECTRONICS [STMicroelectronics]
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STM32WL55JC датащи(HTML) 131 Page - STMicroelectronics

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DS13293 Rev 2
131/147
STM32WL55/54xx
Electrical characteristics
137
5.3.25
Timers characteristics
Parameters given in the following tables are guaranteed by design. Refer to Section 5.3.16:
I/O port characteristics for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).
IDDA(COMP)
Comparator consumption
from VDDA
Ultra-low-
power mode
Static
-
400
600
nA
With 50 kHz ±100 mV
overdrive square signal
-
1200
-
Medium
mode
Static
-
5
7
µA
With 50 kHz ±100 mV
overdrive square signal
-6
-
High-speed
mode
Static
-
70
100
With 50 kHz ±100 mV
overdrive square signal
-75
-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 35: Embedded internal voltage reference.
3. Guaranteed by characterization results.
Table 89. COMP characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 90. TIMx(1) characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)
Timer resolution time
-1
-
tTIMxCLK
fTIMxCLK = 48 MHz
15.625
-
ns
fEXT
Timer external clock frequency
on CH1 to CH4
-0
fTIMxCLK/2
MHz
fTIMxCLK = 48 MHz
0
40
ResTIM
Timer resolution
TIM1, TIM16, TIM17
-
16
bit
TIM2
-
32
tCOUNTER
16-bit counter clock period
-
1
65536
tTIMxCLK
fTIMxCLK = 48 MHz
0.015625
1024
µs
tMAX_COUNT
Maximum possible count with
32-bit counter
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 48 MHz
-
67.10
s
1. TIMx, is used as a general term where x stands for 1, 2, 16 or 17.



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