DLPC4430 datasheet(28/49 Pages) TI

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Table 7-1. Primary Channel/Video-Graphics Processing Delay

Source

Frame Rate Conversion

FRC Type

Formatter Buffer

Total Delay

48 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

50 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

60 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

100 and 120 Hz Graphics

1 Frame

Sync (1:1)

N Frames

1 + N Frames

100 and 120 Hz Graphics

(3D)

1 Frame

Sync (1:2)

M Frames

1 + M Frames

7.3.6 Program Memory Flash/SRAM Interface

The DLPC4430 controller provides three external program memory chip selects:

• PM_CSZ_0 – available for optional SRAM or flash device (≤ 128 Mb)

• PM_CSZ_1 – dedicated CS for boot flash device (ie. Standard NOR-type flash, ≤ 128 Mb)

• PM_CSZ_2 – available for optional SRAM or flash device (≤ 128 Mb)

Flash and SRAM access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 ns

in normal mode and 53.33 ns in low power modes. Wait state program values for typical flash access times are

shown in the Table 7-2.

Table 7-2. Wait State Program Values for Typical Flash Access Times

Normal Mode (1)

Low Power Mode(1)

Formula to Calculate the

Required Wait State Value

= Roundup (Device_Access_Time / 6.7 ns)

= Roundup

(Device_Access_Time / 53.33 ns)

Max Supported Device Access

Time

207 ns

1660 ns

(1)

Assumes a maximum single direction trace length of 75 mm.

Note that when another device such as an SRAM or additional flash is used in conjunction with the boot flash,

care must be taken to keep stub length short and located as close as possible to the flash end of the route.

The DLPC4430 controller provides enough Program Memory Address pins to support a flash or SRAM device

up to 128 Mb. For systems not requiring this capacity, up to two address pins can be used as GPIO instead.

Specifically, the two most significant address bits (i.e. PM_ADDR_22 and PM_ADDR_21) are shared on pins

GPIO_36 and GPIO_35 respectively. Like other GPIO pins, these pins float in a high-impedance input state

following reset; therefore, if these GPIO pins are to be reconfigured as Program Memory Address pins, they

require board-level pull-down resistors to prevent any flash address bits from floating until software is able to

reconfigure the pins from GPIO to Program Memory Address. Also note that until software reconfigures the pins

from GPIO to Program Memory Address, upper portions of flash memory are not accessible.

Table 7-3 shows typical GPIO_35 and GPIO36 pin configuration for various flash sizes.

Table 7-3. Typical GPIO_35 and GPIO_36 Pin Configurations for Various Flash Sizes

FLASH SIZE

GPIO_36 Pin Configuration

GPIO_35 Pin Configuration

32 Mb or less

GPIO_36

GPIO_35

64 Mb

GPIO_36

PM_ADDR_21(1)

128 Mb

PM_ADDR_22(1)

PM_ADDR_21(1)

(1)

Board-level pulldown resistor required.

7.3.7 Calibration and Debug Support

The DLPC4430 controller contains a test point output port, TSTPT_(7:0), which provides selected system

calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch

to outputs when reset is released. The state of these signals is sampled upon the release of system reset

and the captured value configures the test mode until the next time reset is applied. Each test point includes

an internal pull-down resistor and thus external pull-ups are used to modify the default test configuration. The

default configuration (x00) corresponds to the TSTPT_(7:0) outputs being driven low for reduce switching activity

DLPC4430

DLPS223 – DECEMBER 2021

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