DLPC4430 datasheet(11/49 Pages) TI

11 / 49 page

Table 5-1. Pin Functions (continued)

PIN(1)

I/O(2)

DESCRIPTION

NAME

NO.

POWER and GROUND

VDD33

F20, F17, F11, F8,

L21, R21, Y21,

AA19, AA16, AA10,

AA7

POWER

3.3V I/O Power

VDD18

C1, F5, G6, K6,

M5, P5, T5, W6,

AA5, AE1, H5, N6,

T6, AA13, U21, P21,

H21, F14

POWER

1.8V Internal DRAM and LVDS I/O Power

VDD11

F19, F16, F13, F10,

F7, H6, L6, P6,

U6, Y6, AA8, AA11,

AA14, AA17, AA20,

W21, T21, N21, K21,

G21, L11, T11, T16,

L16

POWER

1.15V Core Power

VDD_PLLD

L22

POWER

1.15V DMD clock generator PLL digital power

VSS_PLLD

L23

GROUND

1.15 V DMD clock generator PLL digital ground

VAD_PLLD

K25

POWER

1.8V DMD clock generator PLL analog power

VAS_PLLD

K26

GROUND

1.8V DMD clock generator PLL analog ground

VDD_PLLM1

L26

POWER

1.15V Master-LS clock generator PLL digital power

VSS_PLLM1

M22

GROUND

1.15V Master-LS clock generator PLL digital ground

VAD_PLLM1

L24

POWER

1.8V Master-LS clock generator PLL analog power

VAS_PLLM1

L25

GROUND

1.8V Master-LS clock generator PLL analog ground

VDD_PLLM2

P23

POWER

Master-HS clock generator PLL digital power

VSS_PLLM2

P24

GROUND

Master-HS clock generator PLL digital ground

VAD_PLLM2

R25

POWER

1.8V Master-HS clock generator PLL analog power

VAS_PLLM2

R26

GROUND

1.8V Master-HS clock generator PLL analog ground

VAD_PLLS

R23

POWER

video-2X clock generator PLL analog power

VAS_PLLS

R24

GROUND

video-2X clock generator PLL analog ground

L-VDQPAD_[7:0], R-

VDQPAD_[7:0]

B18, D18, B17, E17,

A18, C18, A17, D17,

AE17, AC17, AF17,

AC18, AB16, AD17,

AB17, AD18

RESERVED

These pins have to be tied directly to ground for normal operation.

CFO_VDD33

AE26

RESERVED

This pin has to be tied directly to 3.3 I/O power (VDD33) for normal operation.

VTEST1, VTEST2,

VTEST3, VTEST4

AB14, AB15, E15,

E16

RESERVED

These pins have to be tied directly to ground for normal operation.

LVDS_AVS1,

LVDS_AVS2

V5, K5

POWER

These pins have to be tied directly to ground for normal operation.

VPGM

AC6

POWER

This pin has to be tied directly to ground for normal operation.

GROUND

A26, A25, A24, B25,

C24, D23, E22, F21,

F18, F15, F12, F9,

F6, E5, D4, C3, B3,

A3, B2, A2, B1, A1

G5, J5, J6, L5, M6,

N5, R5, R6, U5, V6,

W5, Y5, AA6, AB5,

AC4, AD3, AE3,

AF3, AF2, AF1, AA9,

AA12, AA15, AA18,

AA21, AB22, AC23,

AD24, AE24, AF24,

AE25, AF25, AF26,

V21, M21, J21, L15,

L14, L13, L12, M16,

M15, M14, M13,

M12, M11, N16,

N15, N14, N13, N12,

N11, P16, P15, P14,

P13, P12, P11, R16,

R15, R14, R13, R12,

R11, T15, T14, T13,

T12

GROUND

Common ground

(1)

For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

(2)

I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 5-2 for subscript explanation.

(3)

All JTAG signals are LVTTL compatible.

www.ti.com

DLPC4430

DLPS223 – DECEMBER 2021

Submit Document Feedback

Product Folder Links: DLPC4430

DLPC4430 датащи(PDF) 11 Page - Texas Instruments

DLPC4430 датащи(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

датащи скачать

ссылки URL