DLPC4430 datasheet(6/49 Pages) TI

6 / 49 page

Table 5-1. Pin Functions (continued)

PIN(1)

I/O(2)

DESCRIPTION

NAME

NO.

P2_B_6

AB25

Port 2 B Channel Input Pixel Data (bit weight 16)

P2_B_5

AA22

Port 2 B Channel Input Pixel Data (bit weight 8)

P2_B_4

AB24

Port 2 B Channel Input Pixel Data (bit weight 4)

P2_B_3

AC26

Port 2 B Channel Input Pixel Data (bit weight 2)

P2_B_2

AB23

Port 2 B Channel Input Pixel Data (bit weight 1)

P2_B_1

AC25

Port 2 B Channel Input Pixel Data (bit weight 0.5)

P2_B_0

AC24

Port 2 B Channel Input Pixel Data (bit weight 0.25)

P2_C_9

W23

Port 2 C Channel Input Pixel Data (bit weight 128)

P2_C_8

V22

Port 2 B Channel Input Pixel Data (bit weight 64)

P2_C_7

Y26

Port 2 C Channel Input Pixel Data (bit weight 32)

P2_C_6

Y25

Port 2 B Channel Input Pixel Data (bit weight 16)

P2_C_5

Y24

Port 2 C Channel Input Pixel Data (bit weight 8)

P2_C_4

Y23

Port 2 B Channel Input Pixel Data (bit weight 4)

P2_C_3

W22

Port 2 C Channel Input Pixel Data (bit weight 2)

P2_C_2

AA26

Port 2 B Channel Input Pixel Data (bit weight 1)

P2_C_1

AA25

Port 2 C Channel Input Pixel Data (bit weight 0.5)

P2_C_0

AA24

Port 2 B Channel Input Pixel Data (bit weight 0.25)

P2_VSYNC

U22

Port 2 Vertical Sync. This signal includes an internal pull-down. While intended to be associated with Port 2, it can be

programmed for use with Port1.

P2_HSYNC

W26

Port 2 Horizontal Sync. This signal includes an internal pull-down. While intended to be associated with Port 2, it can

be programmed for use with Port1.

ALF INPUT PORT CONTROL

ALF_VSYNC

AF11

Autolock dedicated vertical sync. This signal includes an internal pull-down and uses hysteresis.

ALF_HSYNC

AD11

Autolock dedicated horizontal sync. This signal includes an internal pull-down and uses hysteresis.

ALF_CSYNC

AE11

Autolock dedicated composite sync (sync on green). This signal includes an internal pull-down and uses hysteresis.

DMD RESET and BIAS CONTROL

DADOEZ

AE7

DAD (DLPA200 / DLPA300)Output Enable (active low)

DADADDR_3

AD6

DAD address

DADADDR_2

AE5

DADADDR_1

AF4

DADADDR_0

AB8

DADMODE_1

AD7

DAD modes

DADMODE_0

AE6

DADSEL_1

AE4

DAD select

DADSEL_0

AC7

DADSTRB

AF5

DAD strobe

DAD_INTZ

AC8

DAD interrupt (active low). This signal typically requires an external pull-up and uses hysteresis.

DMD LVDS INTERFACE

DCKA_P

DMD, LVDS I/F channel A, differential clock

DCKA_N

SCA_P

DMD, LVDS I/F channel A, differential serial control

SCA_N

DDA_P_15