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6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements

MIN

MAX

UNIT

fclock

Clock frequency, TCK

MHZ

Cycle time, TCK

100

tW(H)

Pulse duration, high

50% to 50% reference points

(signal)

tW(L)

Pulse duration, low

50% to 50% reference points

(signal)

Transition time, tt= tf/tr

20% to 80% reference points

(signal)

tSU

Setup time, TDI valid before TCK↑

Hold time, TDI valid after TCK↑

tSU

Setup time, TMS1 valid before TCK↑

Hold time, TMS1 valid before TCK↑

6.9 Port 1 Input Pixel Timing Requirements

TEST CONDITIONS

MIN

MAX

UNIT

fclock

Clock frequency, P_CLK1, P_CLK2, P_CLK3 (30-bit bus)

175

MHz

fclock

Clock frequency, P_CLK1, P_CLK2, P_CLK3 (60-bit bus)

141

MHz

Cycle Time, P_CLK1, P_CLK2, P_CLK3

5.714

83.33

tW(H)

Pulse Duration, high

50% to 50% reference points

(signal)

2.3

tW(L)

Pulse Duration, low

50% to 50% reference points

(signal)

2.3

tjp

Clock period jitter, P_CLK1, P_CLK2, P_CLK3

Max ƒclock

See (2)

Transition time, tt=tf/tr, P_CLK1, P_CLK2, P_CLK3

20% to 80% reference points

(signal)

0.6

2.0

Transition time, tt=tf/tr, P1_A(9-0), P1_B(9-0), P1_C(9-0),

P1_HSYNC, P1_VSYNC, P1_DATAEN

20% to 80% reference points

(signal)

0.6

3.0

Transition time, tt=tf/tr, ALF_HSYNC, ALF_VSYNC,

ALF_CSYNC(1)

20% to 80% reference points

(signal)

0.6

3.0

SETUP AND HOLD TIMES

tsu

Setup time, P1_A(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P1_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P1_B(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P1_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P1_C(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P1_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P1_VSYNC, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P1_VSYNC valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P1_HSYNC, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P1_HSYNC valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

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DLPC4430

DLPS223 – DECEMBER 2021

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