DLPC4430 datasheet(8/49 Pages) TI

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Table 5-1. Pin Functions (continued)

PIN(1)

I/O(2)

DESCRIPTION

NAME

NO.

PM_CSZ_0

D13

Input Bus D Data bit 3.

100-Ω internal LVDS termination.

PM_CSZ_1

E12

PM_CSZ_2

A13

Input Bus D Data bit 5.

100-Ω internal LVDS termination.

PM_ADDR_22

(GPIO 36)

A12

PM_ADDR_21

(GPIO 35)

E11

Input Bus D Data bit 10.

100-Ω internal LVDS termination.

PM_ADDR_20

D12

PM_ADDR_19

C12

Input Bus D Data bit 11.

100-Ω internal LVDS termination.

PM_ADDR_18

B11

PM_ADDR_17

A11

Input Bus D Data bit 12.

100-Ω internal LVDS termination.

PM_ADDR_16

D11

PM_ADDR_15

C11

Input Bus D Data bit 13.

100-Ω internal LVDS termination.

PM_ADDR_14

E10

PM_ADDR_13

D10

Input Bus D Data bit 14.

100-Ω internal LVDS termination.

PM_ADDR_12

C10

PM_ADDR_11

Input Bus D Data bit 15.

100-Ω internal LVDS termination.

PM_ADDR_10

PM_ADDR_9

Output Bus A Data bit 0 to DMD.

PM_ADDR_8

PM_ADDR_7

Output Bus A Data bit 1 to DMD.

PM_ADDR_6

PM_ADDR_5

Output Bus A Data bit 2 to DMD.

PM_ADDR_4

PM_ADDR_3

Output Bus A Data bit 3 to DMD.

PM_ADDR_2

PM_ADDR_1

Output Bus A Data bit 4 to DMD.

PM_ADDR_0

PM_WEZ

B12

Output Bus A Data bit 5 to DMD.

PM_OEZ

C13

PM_BLSZ_1

Output Bus A Data bit 6 to DMD.

PM_BLSZ_0

PM_DATA_15

C17

Output Bus A Data bit 7 to DMD.

PM_DATA_14

B16

PM_DATA_13

A16

Output Bus A Data bit 8 to DMD.

PM_DATA_12

A15

PM_DATA_11

B15

Output Bus A Data bit 9 to DMD.

PM_DATA_10

D16

PM_DATA_9

C16

Output Bus A Data bit 10 to DMD.

PM_DATA_8

E14

PM_DATA_7

D15

Output Bus A Data bit 11 to DMD.

PM_DATA_6

C15

PM_DATA_5

B14

Output Bus A Data bit 12 to DMD.

PM_DATA_4

A14

PM_DATA_3

E13

Output Bus A Data bit 13 to DMD.

PM_DATA_2

D14

PM_DATA_1

C14

Output Bus A Data bit 14 to DMD.

PM_DATA_0

B13

PERIPHERAL INTERFACE

IIC0_SCL

A10

I2C Bus 0, Clock. This bus support 400 kHz, fast mode operation. This signal requires an external pull-up to 3.3 V.

The minimum acceptable pull-up value is 1 kΩ. This input is not 5 V tolerant.

IIC0_SDA

B10

2C Bus 0, Data. This bus support 400 kHz, fast mode operation. This signal requires an external pull-up to 3.3 V. The

minimum acceptable pull-up value is 1 kΩ. This input is not 5 V tolerant.

SSP0_CLK

AD4

Synchronous Serial Port 0, clock

DLPC4430

DLPS223 – DECEMBER 2021

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