AT45DB321E datasheet(26/70 Pages) DIALOG

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AT45DB321E

8784L–DFLASH–3/2019

7.2.1

Programming the Security Register

The user programmable portion of the Security Register does not need to be erased before it is programmed.

To program the Security Register, a 4-byte opcode sequence of 9Bh, 00h, 00h, and 00h must be clocked into the device.

After the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user

programmable portion of the Security Register must be clocked in.

After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program

cycle. The programming of the Security Register should take place in a time of t

P, during which time the RDY/BUSY bit in

the Status Register will indicate that the device is busy. If the device is powered-down during the program cycle, then the

contents of the 64-byte user programmable portion of the Security Register cannot be guaranteed.

If the full 64 bytes of data are not clocked in before the CS pin is deasserted, then the values of the byte locations not

clocked in cannot be guaranteed.

Example:

If only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the

user programmable portion of the Security Register cannot be guaranteed. Furthermore, if more than

64 bytes of data is clocked into the device, then the data will wrap back around to the beginning of the

the Security Register.

Warning:

The user programmable portion of the Security Register can only be programmed one time.

Therefore, it is not possible, for example, to only program the first two bytes of the register and then program

the remaining 62 bytes at a later time.

The Program Security Register command utilizes Buffer 1 for processing. Therefore, the contents of Buffer

1 will be altered from its previous state when this command is issued.

Figure 7-4.

Program Security Register

7.2.2

Reading the Security Register

To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last

dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last

byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output

on the SO pin.

Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance

state.

Table 7-7.

Read Security Register

Data

9Bh

00h

Data

n + 1

Data

n + x

Each transition represents eight bits

77h

Data

n + 1

Data

n + x

Each transition represents eight bits

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