AT45DB321E datasheet(7/70 Pages) DIALOG

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AT45DB321E

8784L–DFLASH–3/2019

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated

opcodes are contained in Table 14-1 on page 39 through Table 14-4 on page 40. A valid instruction starts with the falling

edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the

CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address

location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant

Bit (MSB) first.

Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM

buffers. The three address bytes will be comprised of a number of dummy bits and a number of actual device address

bits, with the number of dummy bits varying depending on the operation being performed and the selected device page

size. Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using the

terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. The main

memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0, where PA12 - PA0 denotes the

13 address bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits required to designate

a byte address within the page. Therefore, when using the standard DataFlash page size, a total of 23 address bits are

used.

For the “power of 2” binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the

conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a

buffer. Main memory addressing is referenced using the terminology A21 - A0, where A21 - A9 denotes the 13 address

bits required to designate a page address, and A8 - A0 denotes the nine address bits required to designate a byte

address within a page. Therefore, when using the binary page size, a total of 22 address bits are used.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data

buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 24., Detailed Bit-level

Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each

mode.

5.1

Continuous Array Read (Legacy Command: E8h Opcode)

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized

to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional

addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter

that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed

without the need for additional address sequences. To perform a Continuous Array Read using the standard DataFlash

page size (528 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which

comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 13 bits (PA12 - PA0) of the 23-bit

address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 23-bit

address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the

binary page size

(512 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and four dummy bytes.

The first 13 bits (A21 - A9) of the 22-bit address sequence specify which page of the main memory array to read and the

last nine bits (A8 - A0) of the 22-bit address sequence specify the starting byte address within the page. The dummy

bytes that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional

clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of

data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue

reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover

from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,

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