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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT25SL321 датащи(PDF) 14 Page - Dialog Semiconductor |
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AT25SL321 датащи(HTML) 14 Page - Dialog Semiconductor |
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14 / 82 page  13 AT25SL321 DS-25SL321–112H–2020-10 Note 1. When SRP1, SRP0 = (1,0), a power down, power-up cycle changes SRP1, SRP0 = (0,0). 7.4 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation. When the QE bit is set to a 0 state (factory default) the WP pin and HOLD are enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: Never set The QE bit to a 1 during standard SPI or Dual SPI operation if the WP or HOLD pins are tied directly to the power supply or ground. 7.5 Erase/Program Suspend Status (SUS) The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power down, power-up cycle. Table 7-3. Encoding of the SRP[1:0] Bits in the Status Register SRP1 SRP0 WP Status Register Description 0 0 X Software Protected The register can be written to after a Write Enable instruction, WEL = 1. [Factory Default] 0 1 0 Hardware Protected When WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down Status Register is protected and cannot be written to again until the next power down, power-up cycle(1) 1 1 X One-Time Program Status Register is permanently protected and cannot be written to. |
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