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AT25SL321 датащи(PDF) 68 Page - Dialog Semiconductor |
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AT25SL321 датащи(HTML) 68 Page - Dialog Semiconductor |
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68 / 82 page ![]() 67 AT25SL321 DS-25SL321–112H–2020-10 8.40 Write Security Register (2Fh) The Write Security Register instruction is for changing the values of Security Register bits. Unlike the Write Status Register instruction, the Write Enable instruction is not required before writing Write Security Register instruction. The Write Security Register instruction can change the value of bit1 (LDSO bit) for customer to lock-down the 4 kbit Secured OTP area. Once the LDSO bit is set to “1”, the Secured OTP area cannot be updated any more. The CS must go high exactly at the boundary; otherwise, the instruction are rejected and not executed. Figure 8-63. Write Security Register Instruction for SPI Mode (left) and QPI Mode (right) 8.41 4 kbit Secured OTP It’s for unique identifier to provide 4 kbit one-time-program area for setting device unique serial number which can be set by factory or system customer. See Table 8-13, Secured OTP Address Space. • Security register bit 0 indicates whether the chip is locked by the factory or not. • To program the 4 kbit secured OTP by entering 4 kbit secured OTP mode (with ENSO command) and going through normal program procedure, and then exiting 4 kbit secured OTP mode by writing the EXSO command. • Customer might lock-down bit 1 as ‘1’. See Table 8-13, Secured OTP Address Space. Note. Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4 kbit secured OTP mode, write access to the array is not allowed. Table 8-13. Secured OTP Address Space Address Range Size Standard Customer Lock 000000 ~ 00000F 128-bit ESN (Electrical Serial Number) Determined by customer 000010 ~ 0001FF 3968-bit N/A |
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