AT25QL321 datasheet(24/79 Pages) DIALOG

номер детали	AT25QL321

подробное описание детали	32-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	79 Pages

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AT25QL321

DS-25QL321–131C–5/2017

7.12 Fast Read Quad Output (6Bh)

By using four pins (IO0, IO1, IO2, and IO3), The Fast Read Quad Output instruction allows data to be transferred from the

AT25QL321 at four times the rate of standard SPI devices.

A Quad enable of Status Register-2 must be executed before

the device will accept the Fast Read Quad Output instruction (Status Register bit QE must equal 1).

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical

Characteristics). This is accomplished by adding eight “dummy” clocks after the 24- bit address as shown in Figure 7-

15. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the dummy

clocks, the data value on the SO pin is a “don’t care”. However, the IO0 pin should be high‐impedance prior to the

falling edge of the first data out clock.

Figure 7-15. Fast Read Quad Output instruction (SPI Mode)

7.13 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O instruction reduces cycle overhead through double access using two IO pins: IO0 and IO1.

Continuous read mode

The Fast Read Dual I/O instruction can further reduce cycle overhead through setting the Mode bits (M7-0) after the

input Address bits (A23-0). The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Dual I/O

instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)

are don’t care (“X”), However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

AT25QL321 датащи(PDF) 24 Page - Dialog Semiconductor