The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is

high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CSW04X/AT24CSW08X will return an ACK. If

a valid comparison is not made, the device will NACK.

Note:  While the lower order 16 bytes of the Security register are read‑only, the device will ACK if the Read/Write

Select bit is a logic ‘0’.

Table 6-1. Device Address Byte AT24CSW04X

Memory Region

Device Type Identifier Hardware Address Bits

MSB Memory

Address

R/W Select

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEPROM Array

1

0

1

0

A2

A1

A8

R/W

Security Register and Write

Protection Register

1

0

1

1

A2

A1

A8

R/W

Table 6-2. Device Address Byte AT24CSW08X

Memory Region

Device Type Identifier

Hardware Address

Bit

MSBs Memory Address R/W Select

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEPROM Array

1

0

1

0

A2

A9

A8

R/W

Security Register and

Write Protection Register

1

0

1

1

A2

A9

A8

R/W

Table 6-3. AT24CSW04X Hardware Address Response by Part Number

Part Number Series

Hardware Address Bits

4-Kbit

A2

A1

AT24CSW040

0

0

0

1

1

0

1

1

Note: 

1.

Contact your local sales representative for hardware client address availability.

Table 6-4. AT24CSW08X Hardware Address Response by Part Number

Part Number Series

Hardware Address Bit

8-Kbit

A2

AT24CSW080

0

AT24CSW084(1)

1

Note: 

1.

Contact your local sales representative for hardware client address availability.

For all operations except the current address read, a word address byte must be transmitted to the device

immediately following the device address byte. The word address byte contain a 9-bit (in the case of the

AT24CSW04X/AT24CSW08X

Memory Organization

and its subsidiaries

Datasheet

DS20006426B-page 17