Figure 9-2. Random Read

SCL

SDA

Start

by

Host

Device Address Byte

Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

#

@

A8

0

0

Dummy Write

Start

by

Host

Device Address Byte

Data Word (n)

Stop

by

Host

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

#

@

X

1

0

D7 D6

D5 D4 D3

D2 D1 D0

1

A7 A6

A5

A4

A3 A2 A1

A0

0

ACK

from

Client

ACK

from

Client

ACK

from

Client

NACK

from

Host

(1)

(2)

(1)

(2)

Notes: 

1.

For the AT24CSW04X, the @ indicates the A1 Hardware Address bit which is managed by the ordering code

of the device (see Table 6-3). For the AT24CSW08X, the @ indicates the A9 address bit.

2.

# indicates the hardware address value which is managed by the ordering code of the device (see Table 6-3

and Table 6-4).

9.3

Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus host receives a data

word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the

word address and serially clock out sequential data words. When the maximum memory address is reached, the data

word address will rollover and the sequential read will continue from the beginning of the memory array. All types of

read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start

condition to begin the next sequence.

Figure 9-3. Sequential Read

SCL

SDA

Start

by

Host

ACK

from

Client

ACK

from

Host

Device Address Byte

Data Word (n)

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

#

@

X

1

0

D7 D6

D5 D4 D3

D2 D1 D0

0

ACK

from

Host

NACK

from

Host

Stop

by

Host

ACK

from

Host

Data Word (n+1)

Data Word (n+2)

Data Word (n+x)

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

D7 D6 D5 D4 D3 D2

D1 D0

0

D7 D6 D5 D4 D3 D2 D1 D0

0

D7 D6 D5 D4 D3 D2 D1 D0

1

MSb

MSb

MSb

(1)

(2)

AT24CSW04X/AT24CSW08X

Read Operations

and its subsidiaries

Datasheet

DS20006426B-page 27