7.4

Write Cycle Timing

the internal write cycle to the Start condition of the first device address byte sent to the AT24CSW04X/AT24CSW08X

that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement. During the

internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed.

Figure 7-4. Write Cycle Timing

t

WR

Stop

Condition

Start

Condition

Data Word n

ACK

D0

SDA

Stop

Condition

SCL

8

9

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum t

WR

can only be determined through

the use of an ACK Polling routine.

9

AT24CSW04X/AT24CSW08X

Write Operations

and its subsidiaries

Datasheet

DS20006426B-page 21