These bits allow four levels of protection of the memory array, provided that the WPRE bit is a logic ‘1’. If the

WPRE bit is a logic ‘0’, the state of the WPB[1:0] bits have no impact on device protection. The protected

address ranges are found in Table 8-6.

• Write-Protect Lock Bit (WPRL), Bit 0

This bit is used to permanently lock the current state of the WPR. A logic ‘0’ indicates that the WPR can be

modified, whereas a logic ‘1’ indicates the WPR was locked and can no longer be modified. To safeguard

against accidental locking of the WPR, the D5 bit must match the WPRL bit (D0 bit) sent to the device. If these

bits do not match, the write cycle is aborted and the WPR contents are not modified.

8.2.1

Protected Address Ranges Set by WPB1 and WPB0

The EEPROM array in the AT24CSW04X/AT24CSW08X will be protected from writing in accordance with the WPB1

and WPB0 bit values as long as the WPRE bit is set to logic ‘1’. If the WPRE bit is set to logic ‘0’, no portion of the

EEPROM array will be protected. The combination of these three bits creates five possible levels of protection for the

device. The protected address ranges of the memory are shown in Table 8-6.

Table 8-6. Word Address Byte Requirements for Accessing the Write Protection Register

Protection

Level

WPRE

WPB1

WPB0

Protected Address Range

Unprotected Address Range

4-Kbit

8-Kbit

4-Kbit

8-Kbit

None

0

X

X

None

None

000h‑1FFh

000h‑3FFh

Upper ¼

1

0

0

180h‑1FFh

300h‑3FFh

000h‑17Fh

000h‑2FFh

Upper ½

1

0

1

100h‑1FFh

200h‑3FFh

000h‑0FFh

000h‑1FFh

Upper ¾

1

1

0

080h‑1FFh

100h‑3FFh

000h‑07Fh

000h‑0FFh

Full Array

1

1

1

000h‑1FFh

000h‑3FFh

None

None

8.3

Writing to the Write Protection Register

When writing the WPR, data bit 7 through 4 are used to ensure that a write operation was intentional. For all write

operations to the WPR, bit 6 must be a logic ‘1’ as seen in Table 8-4.

Additionally, data bit 5 must be set in accordance with the D0 bit value (WPRL) as noted below. If the WPR is to

remain unlocked, then the upper nibble sent during the write operation would be 4h and D0 must be a logic ‘0’,

whereas if the WPR is to be permanently locked, the upper nibble would need to be 6h and D0 must be a logic ‘1’. A

mismatch of D5 and the WPRL bit will cause the write cycle to abort.

Sending more than one byte to the AT24CSW04X/AT24CSW08X when trying to write to the WPR will cause the write

cycle to abort and the contents of the WPR will not be changed. Additionally, if the WPR is already locked (WPRL =

1), the write cycle will not execute and the device will be ready for a new operation.

Figure 8-2. Write Protection Register Write

SCL

SDA

Device Address Byte

Reserved Word Address Byte

WPR Contents

Start

by

Host

ACK

from

Client

MSb

MSb

Stop

by

Host

MSb

1

2

3

4

5

6

7

8

9

1

0

1

1

0

0

1

2

3

4

5

6

7

8

9

0

1

D5

0

D3 D2 D1 D0

0

1

1

X

X

X

X

X

X

0

1

2

3

4

5

6

7

8

9

ACK

from

Client

ACK

from

Client

Notes: 

1.

For the AT24CSW04X, the @ indicates the A1 Address bit which is managed by the ordering code of the

device (see Table 6-3). For the AT24CSW08X, the @ indicates the A9 address bit.

2.

# indicates the hardware address value which is managed by the ordering code of the device (see Table 6-3

and Table 6-4).

AT24CSW04X/AT24CSW08X

Write Protection

and its subsidiaries

Datasheet

DS20006426B-page 24