5.3

Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it has

successfully received the data byte by responding with what is known as an Acknowledge (ACK). An ACK is

accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle

followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.

When the AT24CM02 is transmitting data to the host, the host can indicate that it is done receiving data and wants

to end the operation by sending a logic ‘1’ response to the AT24CM02 instead of an ACK response during the ninth

clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the host sending a logic ‘1’ during

the ninth clock cycle, at which point the AT24CM02 will release the SDA line so the host can then generate a Stop

condition.

The transmitting device, which can be the bus host or the Serial EEPROM, must release the SDA line at the

falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the

previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the

transmitter to continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these

requirements.

Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge

SCL

SDA

SDA

Must Be

Stable

SDA

Change

Allowed

SDA

Change

Allowed

Acknowledge

Valid

Stop

Condition

Start

Condition

1

2

8

9

SDA

Must Be

Stable

Acknowledge Window

The transmitting device (Host or Client)

must release the SDA line at this point to allow

the receiving device (Host or Client) to drive the

SDA line low to ACK the previous 8-bit word.

The receiver (Host or Client)

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

5.4

Standby Mode

The AT24CM02 features a low-power Standby mode that is enabled when any one of the following occurs:

• A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).

• A Stop condition is received by the device unless it initiates an internal write cycle (see Write Operations).

• At the completion of an internal write cycle (see Write Operations).

5.5

Software Reset

After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking

SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the

EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the

software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed

by the protocol. Refer to Figure 5-2 for an illustration.

AT24CM02

Device Operation and Communication

Datasheet

DS20006197C-page 14