Figure 7-3. Acknowledge Polling Flowchart

Did

the device

ACK?

Send any

Write

protocol.

Send

Stop

condition

to initiate the

Write cycle.

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0.

Proceed to

next Read or

Write operation.

NO

YES

7.5

Write Cycle Timing

internal write cycle to the Start condition of the first device address byte sent to the AT24CM02 that it subsequently

responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed

write cycle, any attempts to read from or write to the memory array will not be processed.

Figure 7-4. Write Cycle Timing

t

WR

Stop

Condition

Start

Condition

Data Word n

ACK

D0

SDA

Stop

Condition

SCL

8

9

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum t

WR

can only be determined through

the use of an ACK Polling routine.

9

7.6

Write Protection

The AT24CM02 utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory

floating.

Table 7-1. AT24CM02 Write-Protect Behavior

WP Pin Voltage

Part of the Array Protected

Full Array

GND

None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the

start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not

alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup

(tSU.WP) and hold (tHD.WP) timing as shown in Figure 7-5 below. The WP setup time is the amount of time that

the WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the

AT24CM02

Write Operations

Datasheet

DS20006197C-page 19