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AT24CM02 датащи(PDF) 12 Page - Microchip Technology |
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AT24CM02 датащи(HTML) 12 Page - Microchip Technology |
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12 / 34 page ![]() Table 4-4. Power-up Conditions(1) Symbol Parameter Min. Max. Units tPUP Time required after VCC is stable before the device can accept commands 100 - µs VPOR Power-on Reset Threshold Voltage - 1.5 V tPOFF Minimum time at VCC = 0V between power cycles 1 - ms Note: 1. These parameters are characterized but they are not 100% tested in production. If an event occurs in the system where the VCC level supplied to the AT24CM02 drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed. First, drive the VCC pin to GND, waiting at least the minimum tPOFF time, and then perform a new power-up sequence in compliance with the requirements defined in this section. 4.5.2 Pin Capacitance Table 4-5. Pin Capacitance(1) Symbol Test Condition Max. Units Conditions CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN Input Capacitance (A2 and SCL) 6 pF VIN = 0V Note: 1. This parameter is characterized but is not 100% tested in production. 4.5.3 EEPROM Cell Performance Characteristics Table 4-6. EEPROM Cell Performance Characteristics Operation Test Condition Min. Max. Units Write Endurance(1) TA = 25°C, VCC(min.) < VCC < VCC(max.), Byte(2) or Page Write mode 1,000,000 — Write Cycles Data Retention(1) TA = 55°C 100 — Years Notes: 1. Performance is determined through characterization and the qualification process. 2. Due to the memory array architecture, the Write Cycle Endurance is specified for writes in groups of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3). See Internal Writing Methodology for more details on this implementation. AT24CM02 Electrical Characteristics © 2019-2021 Microchip Technology Inc. Datasheet DS20006197C-page 12 |
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