Figure 7-2.  Page Write

SCL

SDA

Start Condition

by Host

ACK

from Client

ACK

from Client

Device Address Byte

First Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

A

2

A

1

A16

0

0 A15 A14 A13 A12 A11 A10 A9 A8 0

ACK

from Client

ACK

from Client

Stop Condition

by Host

ACK

from Client

Second Word Address Byte

Data Word (n)

Data Word (n+x), max of 256 without rollover

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

A7

A6

A5

A4 A3 A2

A1 A0

0 D7 D6 D5 D4 D3 D2 D1 D0 0

D7 D6 D5 D4 D3 D2 D1 D0

0

MSb

MSb

MSb

7.3

Internal Writing Methodology

The AT24CM02 incorporates a built-in error detection and correction (EDC) logic scheme. The EEPROM array is

internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error Correction Code) bits

of EEPROM. These 38 bits are referred to as the internal physical data word. During a read sequence, the EDC logic

compares each 4-byte physical data word with its corresponding six ECC bits. If a single bit out of the 4-byte region

reads incorrectly, the EDC logic will detect the bad bit and replace it with a correct value before the data is serially

clocked out. This architecture significantly improves the reliability of the AT24CM02 compared to an implementation

that does not utilize EDC.

It is important to note that data is always physically written to the part at the internal physical data word level,

regardless of the number of bytes written. Writing single bytes is still possible with the byte write operation, but

internally, the other three bytes within that 4-byte location where the single byte was written, along with the six ECC

bits, will be updated. Due to this architecture, the AT24CM02 EEPROM write endurance is rated at the internal

physical data word level (4-byte word). The system designer needs to optimize the application writing algorithms to

observe these internal word boundaries in order to reach the endurance rating.

7.4

Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to

Serial EEPROM write cycle has completed, so a subsequent operation can be started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves

repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The

device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the

EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart

has been included below in Figure 7-3 to better illustrate this technique.

AT24CM02

Write Operations

Datasheet

DS20006197C-page 18