FXLS90130 datasheet(68/247 Pages) NXP

68 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

11.2.16.4 Background diagnostic mode fragment size (BDM_FRAGSIZE)

The background diagnostic mode fragment size bit sets the number of background

diagnostic command bits and response chips to be sent per Periodic Data Collection

Mode sampling period.

BDM_

FRAGSIZE

BDM command fragment size

(Bits)

BDM response fragment size

(Chips)

Table 110. Background diagnostic mode fragment size (BDM_FRAGSIZE)

In SPI and I2C mode, the BDM_FRAGSIZE bit is readable and writable, but has no

impact on device operation or performance.

In PSI5 mode, the BDM_FRAGSIZE bit is readable and writable, but has no impact on

device operation or performance.

11.2.16.5 Background diagnostic mode enable (BDM_EN)

The background diagnostic mode enable bit enables background diagnostic mode as

described in Table 111. See Section 12.4 for details regarding background diagnostic

mode.

BDM_EN

Background diagnostic mode

Disabled

Enabled

Table 111. Background diagnostic mode enable (BDM_EN)

In SPI and I2C mode, the BDM_EN bit is readable and writable, but has no impact on

device operation or performance.

In PSI5 mode, the BDM_EN bit is readable and writable, but has no impact on device

operation or performance.

11.2.17 PSI5 configuration register (PSI5_CFG)

The PSI5 configuration register is a user programmable OTP register that contains PSI5

specific configuration information. This register is included in the read/write array error

detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$25

PSI5_CFG

SYNC_PD

DAISY_CHAIN

PSI5_ILOW

RESERVED

EMSG_EXT

P_CRC

INIT2_EXT

ASYNC

Unprogrammed OTP Value

FXLS93xxx

Unprogrammed

Default PSI5 Mode

Table 112. PSI5 configuration register (PSI5_CFG)

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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