FXLS90130 datasheet(65/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

PSI5_

ERRLATCH

PSI5 error handling

Error handling is as specified in Section 11.2.2 and Section 13.8.4

Automatic error clearing is disabled and internal errors are latched until reset as

specified in Section 13.8.5

Table 101. PSI5 error latching enable bit (PSI5_ERRLATCH)

11.2.15.3 Simultaneous sampling enable (SS_EN)

In DSI3 mode, the simultaneous sampling enable bit selects between one of two data

latency methods. See Section 12.4.7 for details regarding sample timing.

SS_EN

Data latency

Synchronous Sampling Mode: Latency relative to transmission start time (PDCM_

RSPST)

Simultaneous Sampling Mode: Latency relative to the start of the Periodic Data

Collection Mode command (falling edge)

Table 102. DSI3 simultaneous sampling enable (SS_EN)

In PSI5 mode, the simultaneous sampling enable bit selects between one of two data

latency methods to accommodate synchronized sampling or simultaneous sampling.

SS_EN

Data latency

Synchronous Sampling Mode (Latency relative to Time Slot)

Simultaneous Sampling Mode (Latency relative to sync pulse)

Table 103. PSI5 simultaneous sampling enable (SS_EN)

In SPI mode, the simultaneous sampling enable bit selects between one of two data

latency methods.

SS_EN

Data latency

Synchronous sampling mode: The data for all sources is latent relative to the

falling edge of slave select for the response to the Sensor Data Request for the

corresponding SOURCEID.

Simultaneous sampling mode: The data for all sources is latent relative to the falling

edge of slave select for the response to the Sensor Data Request for SOURCEID_0.

If SOURCEID_0 is disabled, then the data for all SOURCEIDs is latent relative to the

falling edge of slave select for the response to the Sensor Data Request for lowest

enabled SOURCEID register address.

Note: If multiple SOURCEIDs are enabled, sensor data for the higher SOURCEID

SOURCEID register address. If continuous sensor data requests occur without

sensor data requests for the lowest SOURCEID register address, sensor data

will not be updated. Care must be taken by the user to ensure proper data

transmissions.

Table 104. SPI simultaneous sampling enable (SS_EN)

In I2C mode, the simultaneous sampling enable bit is readable and writable but has no

impact on device operation or performance.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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