FXLS90130 datasheet(49/247 Pages) NXP

49 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

Location

Bit

Address

$05

COMMREV

COMMREV[3:0]

Reset Value for DSI3

Reset Value for PSI5

Reset Value for SPI

Reset Value for I2C

Table 69. Communication protocol revision register (COMMREV)

Note: The response to a register write of the COMMREV register is a valid response

with the register contents equal to 0x00.

11.2.4 Margin read status register (MREAD_STAT)

The Margin Read Status register is a read-only register which contains the status for the

user enabled OTP margin read test.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming

Mode.

Location

Bit

Address

$06

MREAD_

STAT

RESERVED

MARGIN_

RD_ACT

MARGIN_

RD_ERR

Reset Value

Table 70. Margin read status register (MREAD_STAT)

Note: The user enabled OTP margin read test is not intended for use in normal

operation. It is intended for use only after user OTP programming during manufacturing.

11.2.4.1 Margin read active status (MARGIN_RD_ACT)

The margin read active status bit is set if a user enabled OTP margin read test is in

process. The status bit is automatically cleared when the OTP margin read test is

complete. See Section 11.2.7.1 for details regarding the user enabled OTP margin read

test.

MARGIN_RD_ACT

Condition

No Margin Read Test is in Process

Margin Read Test is in Process

Table 71. Margin read active status (MARGIN_RD_ACT)

11.2.4.2 Margin read error status (MARGIN_RD_ERR)

The margin read error status bit is set if a user enabled OTP margin read test has failed.

The margin read error status bit is cleared on a read of the MREAD_STAT register. The

margin read error status bit has no impact on device operation or performance. See

Section 11.2.7.1 for details regarding the user enabled OTP margin read test.

MARGIN_RD_ERR

Condition

No Margin Read Test Failure

Margin Read Test Failure

Table 72. Margin read error status (MARGIN_RD_ERR)

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

49 / 247

FXLS90130 датащи(PDF) 49 Page - NXP Semiconductors

FXLS90130 датащи(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL